M-Labs/artiq-zynq
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fixed runtime compilation error

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This commit is contained in:
pca006132 2020-09-01 13:50:25 +08:00
parent d499a5e9b2
commit a1cd56299d
1 changed files with 2 additions and 44 deletions
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46
src/runtime/src/main.rs
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@ -14,14 +14,13 @@ extern crate alloc;
use core::{cmp, str}; use core::{cmp, str};
use log::{info, warn, error}; use log::{info, warn, error};
use libboard_zynq::{timer::GlobalTimer, devc, slcr, mpcore, gic}; use libboard_zynq::{timer::GlobalTimer, mpcore, gic};
use libasync::{task, block_async}; use libasync::{task, block_async};
use libsupport_zynq::ram; use libsupport_zynq::ram;
use libregister::RegisterW;
use nb; use nb;
use void::Void; use void::Void;
use embedded_hal::blocking::delay::DelayMs; use embedded_hal::blocking::delay::DelayMs;
use libconfig::{Config, load_pl}; use libconfig::Config;
mod proto_core_io; mod proto_core_io;
mod proto_async; mod proto_async;
@ -44,45 +43,6 @@ mod mgmt;
mod analyzer; mod analyzer;
mod irq; mod irq;
fn init_gateware() {
// Set up PS->PL clocks
slcr::RegisterBlock::unlocked(|slcr| {
// As we are touching the mux, the clock may glitch, so reset the PL.
slcr.fpga_rst_ctrl.write(
slcr::FpgaRstCtrl::zeroed()
.fpga0_out_rst(true)
.fpga1_out_rst(true)
.fpga2_out_rst(true)
.fpga3_out_rst(true)
);
slcr.fpga0_clk_ctrl.write(
slcr::Fpga0ClkCtrl::zeroed()
.src_sel(slcr::PllSource::IoPll)
.divisor0(8)
.divisor1(1)
);
slcr.fpga_rst_ctrl.write(
slcr::FpgaRstCtrl::zeroed()
);
});
if devc::DevC::new().is_done() {
info!("gateware already loaded");
// Do not load again: assume that the gateware already present is
// what we want (e.g. gateware configured via JTAG before PS
// startup, or by FSBL).
// Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it).
slcr::RegisterBlock::unlocked(|slcr| {
slcr.init_postload_fpga();
});
} else {
// Load from SD card
match load_pl::load_bitstream_from_sd() {
Ok(_) => info!("Bitstream loaded successfully!"),
Err(e) => info!("Failure loading bitstream: {}", e),
}
}
}
fn identifier_read(buf: &mut [u8]) -> &str { fn identifier_read(buf: &mut [u8]) -> &str {
unsafe { unsafe {
pl::csr::identifier::address_write(0); pl::csr::identifier::address_write(0);
@ -191,9 +151,7 @@ pub fn main_core0() {
ram::init_alloc_core0(); ram::init_alloc_core0();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
init_gateware();
info!("detected gateware: {}", identifier_read(&mut [0; 64])); info!("detected gateware: {}", identifier_read(&mut [0; 64]));
let cfg = match Config::new() { let cfg = match Config::new() {
Ok(cfg) => cfg, Ok(cfg) => cfg,
Err(err) => { Err(err) => {