From a1cd56299d1c8faf081930423e63179b527dfea8 Mon Sep 17 00:00:00 2001 From: pca006132 Date: Tue, 1 Sep 2020 13:50:25 +0800 Subject: [PATCH] fixed runtime compilation error --- src/runtime/src/main.rs | 46 ++--------------------------------------- 1 file changed, 2 insertions(+), 44 deletions(-) diff --git a/src/runtime/src/main.rs b/src/runtime/src/main.rs index dd91c0b..49740d1 100644 --- a/src/runtime/src/main.rs +++ b/src/runtime/src/main.rs @@ -14,14 +14,13 @@ extern crate alloc; use core::{cmp, str}; use log::{info, warn, error}; -use libboard_zynq::{timer::GlobalTimer, devc, slcr, mpcore, gic}; +use libboard_zynq::{timer::GlobalTimer, mpcore, gic}; use libasync::{task, block_async}; use libsupport_zynq::ram; -use libregister::RegisterW; use nb; use void::Void; use embedded_hal::blocking::delay::DelayMs; -use libconfig::{Config, load_pl}; +use libconfig::Config; mod proto_core_io; mod proto_async; @@ -44,45 +43,6 @@ mod mgmt; mod analyzer; mod irq; -fn init_gateware() { - // Set up PS->PL clocks - slcr::RegisterBlock::unlocked(|slcr| { - // As we are touching the mux, the clock may glitch, so reset the PL. - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - .fpga0_out_rst(true) - .fpga1_out_rst(true) - .fpga2_out_rst(true) - .fpga3_out_rst(true) - ); - slcr.fpga0_clk_ctrl.write( - slcr::Fpga0ClkCtrl::zeroed() - .src_sel(slcr::PllSource::IoPll) - .divisor0(8) - .divisor1(1) - ); - slcr.fpga_rst_ctrl.write( - slcr::FpgaRstCtrl::zeroed() - ); - }); - if devc::DevC::new().is_done() { - info!("gateware already loaded"); - // Do not load again: assume that the gateware already present is - // what we want (e.g. gateware configured via JTAG before PS - // startup, or by FSBL). - // Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it). - slcr::RegisterBlock::unlocked(|slcr| { - slcr.init_postload_fpga(); - }); - } else { - // Load from SD card - match load_pl::load_bitstream_from_sd() { - Ok(_) => info!("Bitstream loaded successfully!"), - Err(e) => info!("Failure loading bitstream: {}", e), - } - } -} - fn identifier_read(buf: &mut [u8]) -> &str { unsafe { pl::csr::identifier::address_write(0); @@ -191,9 +151,7 @@ pub fn main_core0() { ram::init_alloc_core0(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); - init_gateware(); info!("detected gateware: {}", identifier_read(&mut [0; 64])); - let cfg = match Config::new() { Ok(cfg) => cfg, Err(err) => {