master wrpll: rename sma_pll to wrpll_refclk

gw& fw: add mmcm prefix to drp csr

src/gateware/kasli_soc.py

@@ -258,8 +258,8 @@ class GenericMaster(SoCCore):
         self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
 
         if with_wrpll:
-            self.submodules.sma_pll = wrpll.SMA_PLL(platform.request("sma_clkin"))
-            self.csr_devices.append("sma_pll")
+            self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
+            self.csr_devices.append("wrpll_refclk")
 
             self.submodules.main_dcxo = si549.Si549(platform.request("ddmtd_main_dcxo_i2c"))
             self.csr_devices.append("main_dcxo")

src/gateware/wrpll.py

@@ -126,7 +126,7 @@ class WRPLL(Module, AutoCSR):
         self.submodules.ev = SharedIRQ(self.ref_tag_ev, self.main_tag_ev)
 
 
-class SMA_PLL(Module, AutoCSR):
+class SMAFrequencyMultiplier(Module, AutoCSR):
     def __init__(self, sma_clkin):
         freq = 125e9
         period = 1e9/freq # ns
@@ -139,13 +139,13 @@ class SMA_PLL(Module, AutoCSR):
         self.mmcm_locked = CSRStatus()
         self.mmcm_reset = CSRStorage()
 
-        self.drp_addr = CSRStorage(7)
-        self.drp_in = CSRStorage(16)
-        self.drp_w_en = CSRStorage()
-        self.drp_en = CSRStorage()
-        self.drp_clk = CSRStorage()
-        self.drp_out = CSRStatus(16)
-        self.drp_ready = CSRStatus()
+        self.mmcm_daddr = CSRStorage(7)
+        self.mmcm_din = CSRStorage(16)
+        self.mmcm_dwen = CSRStorage()
+        self.mmcm_den = CSRStorage()
+        self.mmcm_dclk = CSRStorage()
+        self.mmcm_dout = CSRStatus(16)
+        self.mmcm_dready = CSRStatus()
 
         # # #
 
@@ -170,13 +170,13 @@ class SMA_PLL(Module, AutoCSR):
                 p_CLKOUT0_DIVIDE_F=16, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
 
                 # Dynamic Reconfiguration Port
-                i_DADDR = self.drp_addr.storage,
-                i_DI = self.drp_in.storage,
-                i_DWE = self.drp_w_en.storage,
-                i_DEN = self.drp_en.storage,
-                i_DCLK = self.drp_clk.storage,
-                o_DO = self.drp_out.status,
-                o_DRDY = self.drp_ready.status
+                i_DADDR = self.mmcm_daddr.storage,
+                i_DI = self.mmcm_din.storage,
+                i_DWE = self.mmcm_dwen.storage,
+                i_DEN = self.mmcm_den.storage,
+                i_DCLK = self.mmcm_dclk.storage,
+                o_DO = self.mmcm_dout.status,
+                o_DRDY = self.mmcm_dready.status
             ),
             Instance("BUFG", i_I=ref_clk, o_O=self.cd_ref.clk),
             AsyncResetSynchronizer(self.cd_ref, ~self.mmcm_locked.status),

src/libboard_artiq/src/si549.rs

@@ -548,8 +548,8 @@ pub mod wrpll {
     }
 }
 
-#[cfg(has_sma_pll)]
-pub mod sma_pll {
+#[cfg(has_wrpll_refclk)]
+pub mod wrpll_refclk {
     use super::*;
 
     pub struct MmcmSetting {
@@ -568,45 +568,45 @@ pub mod sma_pll {
 
     fn one_clock_cycle(timer: &mut GlobalTimer) {
         unsafe {
-            csr::sma_pll::drp_clk_write(1);
+            csr::wrpll_refclk::mmcm_dclk_write(1);
             timer.delay_us(1);
-            csr::sma_pll::drp_clk_write(0);
+            csr::wrpll_refclk::mmcm_dclk_write(0);
             timer.delay_us(1);
         }
     }
 
     fn set_addr(address: u8) {
         unsafe {
-            csr::sma_pll::drp_addr_write(address);
+            csr::wrpll_refclk::mmcm_daddr_write(address);
         }
     }
 
     fn set_data(value: u16) {
         unsafe {
-            csr::sma_pll::drp_in_write(value);
+            csr::wrpll_refclk::mmcm_din_write(value);
         }
     }
 
     fn set_enable(en: bool) {
         unsafe {
             let val = if en { 1 } else { 0 };
-            csr::sma_pll::drp_en_write(val);
+            csr::wrpll_refclk::mmcm_den_write(val);
         }
     }
 
     fn set_write_enable(en: bool) {
         unsafe {
             let val = if en { 1 } else { 0 };
-            csr::sma_pll::drp_w_en_write(val);
+            csr::wrpll_refclk::mmcm_dwen_write(val);
         }
     }
 
     fn get_data() -> u16 {
-        unsafe { csr::sma_pll::drp_out_read() }
+        unsafe { csr::wrpll_refclk::mmcm_dout_read() }
     }
 
     fn drp_ready() -> bool {
-        unsafe { csr::sma_pll::drp_ready_read() == 1 }
+        unsafe { csr::wrpll_refclk::mmcm_dready_read() == 1 }
     }
 
     fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
@@ -642,7 +642,7 @@ pub mod sma_pll {
     fn reset(rst: bool) {
         unsafe {
             let val = if rst { 1 } else { 0 };
-            csr::sma_pll::mmcm_reset_write(val)
+            csr::wrpll_refclk::mmcm_reset_write(val)
         }
     }
 
@@ -667,7 +667,7 @@ pub mod sma_pll {
         // wait for the mmcm to lock
         timer.delay_us(100);
 
-        let locked = unsafe { csr::sma_pll::mmcm_locked_read() == 1 };
+        let locked = unsafe { csr::wrpll_refclk::mmcm_locked_read() == 1 };
         if !locked {
             return Err("failed to generate 125Mhz ref clock from SMA CLKIN");
         }