master: fix typos, missing imports

src/gateware/zc706.py

@@ -254,13 +254,13 @@ class _MasterBase(SoCCore):
             memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
             self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
             self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
-        self.config["has_drtio"] = None
+        self.rustc_cfg["has_drtio"] = None
-        self.config["has_drtio_routing"] = None
+        self.rustc_cfg["has_drtio_routing"] = None
         self.add_csr_group("drtio", drtio_csr_group)
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
 
-        self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
+        self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
 
         if use_si5324_33:
             self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
@@ -286,6 +286,10 @@ class _MasterBase(SoCCore):
             platform.add_false_path_constraints(
                 self.ps7.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
 
+        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
+        self.csr_devices.append("rtio_crg")
+        fix_serdes_timing_path(self.platform)
+
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
         self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
@@ -438,6 +442,10 @@ class _SatelliteBase(SoCCore):
             platform.add_false_path_constraints(
                 self.ps7.cd_sys.clk, gtx.rxoutclk)
 
+        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
+        self.csr_devices.append("rtio_crg")
+        fix_serdes_timing_path(self.platform)
+
     def add_rtio(self, rtio_channels):
         # few changes from base add_rtio - moved tsc, no core
 
@@ -605,17 +613,12 @@ class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
 class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
     def __init__(self, acpki):
         _MasterBase.__init__(self, acpki, use_si5324_33=True)
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
+
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
     def __init__(self, acpki):
         _SatelliteBase.__init__(self, acpki, use_si5324_33=True)
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
         _NIST_CLOCK_RTIO.__init__(self)
 
 class NIST_QC2(ZC706, _NIST_QC2_RTIO):
@@ -626,17 +629,11 @@ class NIST_QC2(ZC706, _NIST_QC2_RTIO):
 class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
     def __init__(self, acpki):
         _MasterBase.__init__(self, acpki, use_si5324_33=True)
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
         _NIST_QC2_RTIO.__init__(self)
 
 class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
     def __init__(self, acpki):
         _SatelliteBase.__init__(self, acpki, use_si5324_33=True)
-        self.submodules.rtio_crg = _RTIOClockMultiplier(self.sys_clk_freq)
-        self.csr_devices.append("rtio_crg")
-        fix_serdes_timing_path(self.platform)
         _NIST_QC2_RTIO.__init__(self)
 
 

src/runtime/src/main.rs

@@ -22,7 +22,7 @@ use void::Void;
 use embedded_hal::blocking::delay::DelayMs;
 use libconfig::Config;
 use libcortex_a9::{l2c::enable_l2_cache, mutex::Mutex};
-use libboard_artiq::{logger, identifier_read, init_gateware, pl};
+use libboard_artiq::{logger, identifier_read, init_gateware, pl, drtio_routing};
 #[cfg(has_si5324)]
 use libboard_artiq::si5324;
 
@@ -95,11 +95,11 @@ fn init_rtio(timer: &mut GlobalTimer, cfg: &Config) {
 fn init_drtio(timer: &mut GlobalTimer)
 {
     unsafe {
-        csr::drtio_transceiver::stable_clkin_write(1);
+        pl::csr::drtio_transceiver::stable_clkin_write(1);
     }
     timer.delay_ms(2); // wait for CPLL/QPLL lock
     unsafe {
-        csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
+        pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
     }
 }
 
@@ -188,7 +188,8 @@ pub fn main_core0() {
     // before, mutex was on io, but now that io isn't used...?
     let aux_mutex: Mutex<bool> = Mutex::new(false);
     #[cfg(has_drtio)]
-    let drtio_routing_table = RefCell::new(drtio_routing::config_routing_table(csr::DRTIO.len(), cfg));
+    let drtio_routing_table = RefCell::new(
+        drtio_routing::config_routing_table(pl::csr::DRTIO.len(), cfg));
     #[cfg(not(has_drtio))]
     let drtio_routing_table = RefCell::new(drtio_routing::RoutingTable::default_empty());
     let up_destinations = RefCell::new([false; drtio_routing::DEST_COUNT]);
@@ -197,7 +198,7 @@ pub fn main_core0() {
     #[cfg(has_drtio)]
     init_drtio(&mut timer);
 
-    rtio_mgt::startup()
+    rtio_mgt::startup();
     init_rtio(&mut timer, &cfg);
     task::spawn(report_async_rtio_errors());
 

src/runtime/src/moninj.rs

@@ -3,7 +3,7 @@ use alloc::collections::BTreeMap;
 use log::{debug, info, warn};
 use void::Void;
 
-use board_artiq::drtio_routing;
+use libboard_artiq::drtio_routing;
 
 use libboard_zynq::{smoltcp, timer::GlobalTimer, time::Milliseconds};
 use libasync::{task, smoltcp::TcpStream, block_async, nb};
@@ -14,7 +14,6 @@ use num_traits::{FromPrimitive, ToPrimitive};
 use futures::{pin_mut, select_biased, FutureExt};
 
 use crate::proto_async::*;
-use crate::pl::csr;
 
 
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
@@ -22,7 +21,6 @@ pub enum Error {
     NetworkError(smoltcp::Error),
     UnexpectedPattern,
     UnrecognizedPacket,
-
 }
 
 pub type Result<T> = core::result::Result<T, Error>;
@@ -59,11 +57,12 @@ enum DeviceMessage {
 
 #[cfg(has_drtio)]
 mod remote_moninj {
-    use drtioaux;
+    use libboard_artiq::drtioaux;
-    use rtio_mgt::drtio;
+    use crate::rtio_mgt::drtio;
-    use libcortexa9::Mutex;
+    use libcortex_a9::mutex::Mutex;
+    use log::error;
 
-    pub fn read_probe( aux_mutex: &Mutex, linkno: u8, destination: u8, channel: u16, probe: u8) -> u32 {
+    pub fn read_probe(aux_mutex: &Mutex, linkno: u8, destination: u8, channel: u16, probe: u8) -> u32 {
         let reply = drtio::aux_transact(aux_mutex, linkno, &drtioaux::Packet::MonitorRequest { 
             destination: destination,
             channel: channel,
@@ -103,7 +102,9 @@ mod remote_moninj {
 }
 
 mod local_moninj {
-    fn read_probe(channel: i32, probe: i8) -> i32 {
+    use libboard_artiq::pl::csr;
+
+    pub fn read_probe(channel: i32, probe: i8) -> i32 {
         unsafe {
             csr::rtio_moninj::mon_chan_sel_write(channel as _);
             csr::rtio_moninj::mon_probe_sel_write(probe as _);
@@ -112,7 +113,7 @@ mod local_moninj {
         }
     }
 
-    fn inject(channel: i32, overrd: i8, value: i8) {
+    pub fn inject(channel: i32, overrd: i8, value: i8) {
         unsafe {
             csr::rtio_moninj::inj_chan_sel_write(channel as _);
             csr::rtio_moninj::inj_override_sel_write(overrd as _);
@@ -120,7 +121,7 @@ mod local_moninj {
         }
     }
 
-    fn read_injection_status(channel: i32, overrd: i8) -> i8 {
+    pub fn read_injection_status(channel: i32, overrd: i8) -> i8 {
         unsafe {
             csr::rtio_moninj::inj_chan_sel_write(channel as _);
             csr::rtio_moninj::inj_override_sel_write(overrd as _);

src/runtime/src/rtio_mgt.rs

@@ -1,16 +1,16 @@
 use core::cell::RefCell;
-use board_artiq::pl::csr;
-#[cfg(has_drtio)]
 use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
-use embedded_hal::blocking::delay::DelayMs;
+use libboard_artiq::{pl::csr, drtio_routing};
-use board_artiq::drtio_routing;
 use libcortex_a9::mutex::Mutex;
-use libasync::{task, delay::delay};
+
 
 #[cfg(has_drtio)]
 pub mod drtio {
     use super::*;
-    use drtioaux;
+    use libboard_artiq::drtioaux;
+    use log::{warn, error, info};
+    use embedded_hal::blocking::delay::DelayMs;
+    use libasync::{task, delay};
 
     pub fn startup(aux_mutex: &Mutex,
             routing_table: &RefCell<drtio_routing::RoutingTable>,
@@ -55,7 +55,7 @@ pub mod drtio {
         recv_aux_timeout(linkno, 200, timer).await
     }
 
-    async fn drain_buffer(linkno: u8, draining_time: Milliseconds) {
+    async fn drain_buffer(linkno: u8, draining_time: Milliseconds, timer: GlobalTimer) {
         let max_time = timer.get_time() + draining_time;
         loop {
             if timer.get_time() > max_time {
@@ -191,7 +191,7 @@ pub mod drtio {
         up_destinations[destination as usize]
     }
 
-    async fn destination_survey(io: &Io, aux_mutex: &Mutex, routing_table: &drtio_routing::RoutingTable,
+    async fn destination_survey(aux_mutex: &Mutex, routing_table: &drtio_routing::RoutingTable,
             up_links: &[bool],
             up_destinations: &RefCell<[bool; drtio_routing::DEST_COUNT]>,
             timer: GlobalTimer) {
@@ -208,7 +208,7 @@ pub mod drtio {
                 let linkno = hop - 1;
                 if destination_up(up_destinations, destination).await {
                     if up_links[linkno as usize] {
-                        let reply = aux_transact(io, aux_mutex, linkno, &drtioaux::Packet::DestinationStatusRequest {
+                        let reply = aux_transact(aux_mutex, linkno, &drtioaux::Packet::DestinationStatusRequest {
                             destination: destination
                         }, timer).await;
                         match reply {
@@ -229,7 +229,7 @@ pub mod drtio {
                     }
                 } else {
                     if up_links[linkno as usize] {
-                        let reply = aux_transact(io, aux_mutex, linkno, &drtioaux::Packet::DestinationStatusRequest {
+                        let reply = aux_transact(aux_mutex, linkno, &drtioaux::Packet::DestinationStatusRequest {
                             destination: destination
                         }, timer).await;
                         match reply {
@@ -247,7 +247,7 @@ pub mod drtio {
         }
     }
 
-    pub async fn link_thread(io: Io, aux_mutex: &Mutex,
+    pub async fn link_thread(aux_mutex: &Mutex,
             routing_table: &drtio_routing::RoutingTable,
             up_destinations: &RefCell<[bool; drtio_routing::DEST_COUNT]>,
             timer: GlobalTimer) {
@@ -327,7 +327,7 @@ pub mod drtio {
     use super::*;
 
     pub fn startup(_aux_mutex: &Mutex, _routing_table: &RefCell<drtio_routing::RoutingTable>,
-        _up_destinations: &RefCell<[bool; drtio_routing::DEST_COUNT]>, _timer:GlobalTimer) {}
+        _up_destinations: &RefCell<[bool; drtio_routing::DEST_COUNT]>, _timer: GlobalTimer) {}
     pub fn reset(_aux_mutex: &Mutex, _timer: GlobalTimer) {}
 }