M-Labs/artiq-zynq
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rtio_clocking: brought on par with mainline ARTIQ

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This commit is contained in:
mwojcik 2021-10-28 12:33:43 +08:00
parent d772a94265
commit 90b6dd3e85
1 changed files with 25 additions and 21 deletions
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46
src/runtime/src/rtio_clocking.rs
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@ -13,6 +13,7 @@ use libboard_artiq::si5324;
#[derive(Debug, PartialEq, Copy, Clone)] #[derive(Debug, PartialEq, Copy, Clone)]
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]
pub enum RtioClock { pub enum RtioClock {
Default,
Int_125, Int_125,
Int_100, Int_100,
Int_150, Int_150,
@ -32,12 +33,15 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
"ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125, "ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
"ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125, "ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
"ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125, "ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
_ => RtioClock::Int_125 _ => {
warn!("Unrecognised rtio_clock setting. Falling back to default.");
RtioClock::Int_125
}
} }
} }
else { else {
info!("error reading configuration. Using default internal 125MHz clock"); info!("error reading configuration. Falling back to default.");
RtioClock::Int_125 RtioClock::Default
} }
} }
@ -46,11 +50,11 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
#[cfg(has_rtio_crg_clock_sel)] #[cfg(has_rtio_crg_clock_sel)]
let clock_sel = match _clk { let clock_sel = match _clk {
RtioClock::Ext0_Bypass => { RtioClock::Ext0_Bypass => {
info!("using bypassed external clock"); info!("Using bypassed external clock");
1 1
}, },
x => { x => {
info!("using clock: {:?}", x); info!("Using internal RTIO clock");
0 0
} }
}; };
@ -92,23 +96,23 @@ fn init_drtio(timer: &mut GlobalTimer)
#[cfg(has_si5324)] #[cfg(has_si5324)]
fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) { fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
let mut si5324_settings: Option<si5324::FrequencySettings> = None; let si5324_settings = match clk {
// 125MHz output, from crystal, 7 Hz _ => { // 125MHz output, from crystal, 7 Hz, default, also covers RtioClock::Int_125
if si5324_settings.is_none() || clk == RtioClock::Int_125 { info!("using internal 125MHz RTIO clock");
info!("using internal 125MHz RTIO clock"); si5324::FrequencySettings {
si5324_settings = Some(si5324::FrequencySettings { n1_hs : 10,
n1_hs : 10, nc1_ls : 4,
nc1_ls : 4, n2_hs : 10,
n2_hs : 10, n2_ls : 19972,
n2_ls : 19972, n31 : 4565,
n31 : 4565, n32 : 4565,
n32 : 4565, bwsel : 4,
bwsel : 4, crystal_ref: true
crystal_ref: true }
}); }
} };
let si5324_ref_input = si5324::Input::Ckin2; let si5324_ref_input = si5324::Input::Ckin2;
si5324::setup(i2c, &si5324_settings.unwrap(), si5324_ref_input, timer).expect("cannot initialize Si5324"); si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) { pub fn init(timer: &mut GlobalTimer, cfg: &Config) {