satman: add dma support
This commit is contained in:
parent
4b1ce1a6ff
commit
908dfc780e
src
@ -1,6 +1,9 @@
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use core_io::{Error as IoError, Read, Write};
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use core_io::{Error as IoError, Read, Write};
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use io::proto::{ProtoRead, ProtoWrite};
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use io::proto::{ProtoRead, ProtoWrite};
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/* 512 (max size) - 4 (CRC) - 1 (packet ID) - 1 (destination) - 4 (trace ID) - 1 (last) - 2 (length) */
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pub const DMA_TRACE_MAX_SIZE: usize = 499;
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#[derive(Debug)]
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#[derive(Debug)]
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pub enum Error {
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pub enum Error {
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UnknownPacket(u8),
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UnknownPacket(u8),
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@ -132,6 +135,39 @@ pub enum Packet {
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SpiBasicReply {
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SpiBasicReply {
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succeeded: bool,
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succeeded: bool,
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},
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},
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DmaAddTraceRequest {
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destination: u8,
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id: u32,
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last: bool,
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length: u16,
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trace: [u8; DMA_TRACE_MAX_SIZE]
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},
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DmaAddTraceReply {
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succeeded: bool
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},
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DmaRemoveTraceRequest {
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destination: u8,
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id: u32
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},
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DmaRemoveTraceReply {
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succeeded: bool
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},
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DmaPlaybackRequest {
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destination: u8,
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id: u32,
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timestamp: u64
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},
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DmaPlaybackReply {
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succeeded: bool
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},
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DmaPlaybackStatus {
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destination: u8,
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id: u32,
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error: u8,
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channel: u32,
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timestamp: u64
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},
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}
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}
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impl Packet {
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impl Packet {
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@ -262,6 +298,47 @@ impl Packet {
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succeeded: reader.read_bool()?,
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succeeded: reader.read_bool()?,
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},
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},
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0xb0 => {
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let destination = reader.read_u8()?;
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let id = reader.read_u32()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut trace: [u8; DMA_TRACE_MAX_SIZE] = [0; DMA_TRACE_MAX_SIZE];
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reader.read_exact(&mut trace[0..length as usize])?;
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Packet::DmaAddTraceRequest {
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destination: destination,
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id: id,
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last: last,
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length: length as u16,
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trace: trace,
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}
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},
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0xb1 => Packet::DmaAddTraceReply {
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succeeded: reader.read_bool()?
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},
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0xb2 => Packet::DmaRemoveTraceRequest {
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destination: reader.read_u8()?,
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id: reader.read_u32()?
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},
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0xb3 => Packet::DmaRemoveTraceReply {
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succeeded: reader.read_bool()?
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},
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0xb4 => Packet::DmaPlaybackRequest {
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destination: reader.read_u8()?,
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id: reader.read_u32()?,
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timestamp: reader.read_u64()?
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},
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0xb5 => Packet::DmaPlaybackReply {
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succeeded: reader.read_bool()?
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},
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0xb6 => Packet::DmaPlaybackStatus {
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destination: reader.read_u8()?,
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id: reader.read_u32()?,
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error: reader.read_u8()?,
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channel: reader.read_u32()?,
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timestamp: reader.read_u64()?
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},
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ty => return Err(Error::UnknownPacket(ty)),
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ty => return Err(Error::UnknownPacket(ty)),
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})
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})
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}
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}
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@ -448,6 +525,64 @@ impl Packet {
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writer.write_u8(0x95)?;
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writer.write_u8(0x95)?;
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writer.write_bool(succeeded)?;
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writer.write_bool(succeeded)?;
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}
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}
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Packet::DmaAddTraceRequest {
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destination,
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id,
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last,
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trace,
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length
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} => {
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writer.write_u8(0xb0)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_bool(last)?;
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// trace may be broken down to fit within drtio aux memory limit
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// will be reconstructed by satellite
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writer.write_u16(length)?;
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writer.write_all(&trace[0..length as usize])?;
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}
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Packet::DmaAddTraceReply { succeeded } => {
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writer.write_u8(0xb1)?;
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writer.write_bool(succeeded)?;
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}
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Packet::DmaRemoveTraceRequest { destination, id } => {
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writer.write_u8(0xb2)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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}
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Packet::DmaRemoveTraceReply { succeeded } => {
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writer.write_u8(0xb3)?;
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writer.write_bool(succeeded)?;
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}
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Packet::DmaPlaybackRequest {
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destination,
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id,
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timestamp
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} => {
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writer.write_u8(0xb4)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_u64(timestamp)?;
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}
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Packet::DmaPlaybackReply { succeeded } => {
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writer.write_u8(0xb5)?;
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writer.write_bool(succeeded)?;
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}
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Packet::DmaPlaybackStatus {
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destination,
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id,
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error,
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channel,
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timestamp
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} => {
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writer.write_u8(0xb6)?;
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writer.write_u8(destination)?;
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writer.write_u32(id)?;
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writer.write_u8(error)?;
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writer.write_u32(channel)?;
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writer.write_u64(timestamp)?;
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}
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}
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}
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Ok(())
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Ok(())
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}
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}
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164
src/satman/src/dma.rs
Normal file
164
src/satman/src/dma.rs
Normal file
@ -0,0 +1,164 @@
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use libcortex_a9::cache::dcci_slice;
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use libboard_artiq::pl::csr;
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use alloc::{vec::Vec, collections::btree_map::BTreeMap};
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const ALIGNMENT: usize = 64;
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#[derive(Debug, PartialEq)]
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enum ManagerState {
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Idle,
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Playback
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}
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pub struct RtioStatus {
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pub id: u32,
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pub error: u8,
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pub channel: u32,
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pub timestamp: u64
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}
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pub enum Error {
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IdNotFound,
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PlaybackInProgress,
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EntryNotComplete
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}
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#[derive(Debug)]
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struct Entry {
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trace: Vec<u8>,
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padding_len: usize,
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complete: bool
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}
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#[derive(Debug)]
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pub struct Manager {
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entries: BTreeMap<u32, Entry>,
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state: ManagerState,
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currentid: u32
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}
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impl Manager {
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pub fn new() -> Manager {
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// in case Manager is created during a DMA in progress
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// wait for it to end
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unsafe {
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while csr::rtio_dma::enable_read() != 0 {}
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}
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Manager {
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entries: BTreeMap::new(),
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currentid: 0,
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state: ManagerState::Idle,
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}
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}
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pub fn add(&mut self, id: u32, last: bool, trace: &[u8], trace_len: usize) -> Result<(), Error> {
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let entry = match self.entries.get_mut(&id) {
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Some(entry) => {
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if entry.complete {
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// replace entry
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self.entries.remove(&id);
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self.entries.insert(id, Entry {
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trace: Vec::new(),
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padding_len: 0,
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complete: false });
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self.entries.get_mut(&id).unwrap()
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} else {
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entry
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}
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},
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None => {
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self.entries.insert(id, Entry {
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trace: Vec::new(),
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padding_len: 0,
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complete: false });
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self.entries.get_mut(&id).unwrap()
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},
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};
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entry.trace.extend(&trace[0..trace_len]);
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if last {
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entry.trace.push(0);
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let data_len = entry.trace.len();
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// Realign.
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entry.trace.reserve(ALIGNMENT - 1);
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let padding = ALIGNMENT - entry.trace.as_ptr() as usize % ALIGNMENT;
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let padding = if padding == ALIGNMENT { 0 } else { padding };
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for _ in 0..padding {
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// Vec guarantees that this will not reallocate
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entry.trace.push(0)
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}
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for i in 1..data_len + 1 {
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entry.trace[data_len + padding - i] = entry.trace[data_len - i]
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}
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entry.complete = true;
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entry.padding_len = padding;
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dcci_slice(&entry.trace);
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}
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Ok(())
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}
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pub fn erase(&mut self, id: u32) -> Result<(), Error> {
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match self.entries.remove(&id) {
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Some(_) => Ok(()),
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None => Err(Error::IdNotFound)
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}
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}
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pub fn playback(&mut self, id: u32, timestamp: u64) -> Result<(), Error> {
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if self.state != ManagerState::Idle {
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return Err(Error::PlaybackInProgress);
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}
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let entry = match self.entries.get(&id){
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Some(entry) => entry,
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None => { return Err(Error::IdNotFound); }
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};
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if !entry.complete {
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return Err(Error::EntryNotComplete);
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}
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let ptr = entry.trace[entry.padding_len..].as_ptr();
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assert!(ptr as u32 % 64 == 0);
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self.state = ManagerState::Playback;
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self.currentid = id;
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unsafe {
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csr::rtio_dma::base_address_write(ptr as u32);
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csr::rtio_dma::time_offset_write(timestamp as u64);
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csr::cri_con::selected_write(1);
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csr::rtio_dma::enable_write(1);
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// playback has begun here, for status call check_state
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}
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Ok(())
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}
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pub fn check_state(&mut self) -> Option<RtioStatus> {
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if self.state != ManagerState::Playback {
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// nothing to report
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return None;
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}
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let dma_enable = unsafe { csr::rtio_dma::enable_read() };
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if dma_enable != 0 {
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return None;
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} else {
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self.state = ManagerState::Idle;
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unsafe {
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csr::cri_con::selected_write(0);
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let error = csr::rtio_dma::error_read();
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let channel = csr::rtio_dma::error_channel_read();
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let timestamp = csr::rtio_dma::error_timestamp_read();
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if error != 0 {
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csr::rtio_dma::error_write(1);
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}
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return Some(RtioStatus {
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id: self.currentid,
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error: error,
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channel: channel,
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timestamp: timestamp });
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}
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}
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}
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}
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@ -36,8 +36,10 @@ use libcortex_a9::{asm, interrupt_handler,
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spin_lock_yield};
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spin_lock_yield};
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use libregister::{RegisterR, RegisterW};
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use libregister::{RegisterR, RegisterW};
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use libsupport_zynq::ram;
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use libsupport_zynq::ram;
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use dma::Manager as DmaManager;
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mod repeater;
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mod repeater;
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mod dma;
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fn drtiosat_reset(reset: bool) {
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fn drtiosat_reset(reset: bool) {
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unsafe {
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unsafe {
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@ -92,6 +94,7 @@ fn process_aux_packet(
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packet: drtioaux::Packet,
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packet: drtioaux::Packet,
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timer: &mut GlobalTimer,
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timer: &mut GlobalTimer,
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i2c: &mut I2c,
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i2c: &mut I2c,
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dma_manager: &mut DmaManager
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) -> Result<(), drtioaux::Error> {
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) -> Result<(), drtioaux::Error> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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// and u16 otherwise; hence the `as _` conversion.
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@ -409,6 +412,38 @@ fn process_aux_packet(
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)
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)
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}
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}
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drtioaux::Packet::DmaAddTraceRequest {
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destination: _destination,
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id,
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last,
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length,
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trace
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} => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = dma_manager.add(id, last, &trace, length as usize).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::DmaAddTraceReply { succeeded: succeeded })
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}
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drtioaux::Packet::DmaRemoveTraceRequest {
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destination: _destination,
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id
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} => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = dma_manager.erase(id).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::DmaRemoveTraceReply { succeeded: succeeded })
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}
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drtioaux::Packet::DmaPlaybackRequest {
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destination: _destination,
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id,
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timestamp
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} => {
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forward!(_routing_table, _destination, *_rank, _repeaters, &packet, timer);
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let succeeded = dma_manager.playback(id, timestamp).is_ok();
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drtioaux::send(0,
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&drtioaux::Packet::DmaPlaybackReply { succeeded: succeeded })
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}
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_ => {
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_ => {
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warn!("received unexpected aux packet");
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warn!("received unexpected aux packet");
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Ok(())
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Ok(())
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@ -422,10 +457,11 @@ fn process_aux_packets(
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rank: &mut u8,
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rank: &mut u8,
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timer: &mut GlobalTimer,
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timer: &mut GlobalTimer,
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i2c: &mut I2c,
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i2c: &mut I2c,
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dma_manager: &mut DmaManager
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) {
|
) {
|
||||||
let result = drtioaux::recv(0).and_then(|packet| {
|
let result = drtioaux::recv(0).and_then(|packet| {
|
||||||
if let Some(packet) = packet {
|
if let Some(packet) = packet {
|
||||||
process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c)
|
process_aux_packet(repeaters, routing_table, rank, packet, timer, i2c, dma_manager)
|
||||||
} else {
|
} else {
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
@ -598,13 +634,18 @@ pub extern "C" fn main_core0() -> i32 {
|
|||||||
si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
|
si5324::siphaser::calibrate_skew(&mut timer).expect("failed to calibrate skew");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// DMA manager created here, so when link is dropped, all DMA traces
|
||||||
|
// are cleared out for a clean slate on subsequent connections,
|
||||||
|
// without a manual intervention.
|
||||||
|
let mut dma_manager = DmaManager::new();
|
||||||
|
|
||||||
drtioaux::reset(0);
|
drtioaux::reset(0);
|
||||||
drtiosat_reset(false);
|
drtiosat_reset(false);
|
||||||
drtiosat_reset_phy(false);
|
drtiosat_reset_phy(false);
|
||||||
|
|
||||||
while drtiosat_link_rx_up() {
|
while drtiosat_link_rx_up() {
|
||||||
drtiosat_process_errors();
|
drtiosat_process_errors();
|
||||||
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c);
|
process_aux_packets(&mut repeaters, &mut routing_table, &mut rank, &mut timer, &mut i2c, &mut dma_manager);
|
||||||
#[allow(unused_mut)]
|
#[allow(unused_mut)]
|
||||||
for mut rep in repeaters.iter_mut() {
|
for mut rep in repeaters.iter_mut() {
|
||||||
rep.service(&routing_table, rank, &mut timer);
|
rep.service(&routing_table, rank, &mut timer);
|
||||||
@ -621,6 +662,18 @@ pub extern "C" fn main_core0() -> i32 {
|
|||||||
error!("aux packet error: {:?}", e);
|
error!("aux packet error: {:?}", e);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
if let Some(status) = dma_manager.check_state() {
|
||||||
|
info!("playback done, error: {}, channel: {}, timestamp: {}", status.error, status.channel, status.timestamp);
|
||||||
|
if let Err(e) = drtioaux::send(0, &drtioaux::Packet::DmaPlaybackStatus {
|
||||||
|
destination: rank,
|
||||||
|
id: status.id,
|
||||||
|
error: status.error,
|
||||||
|
channel: status.channel,
|
||||||
|
timestamp: status.timestamp
|
||||||
|
}) {
|
||||||
|
error!("error sending DMA playback status: {:?}", e);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
drtiosat_reset_phy(true);
|
drtiosat_reset_phy(true);
|
||||||
|
Loading…
Reference in New Issue
Block a user