M-Labs/artiq-zynq
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core1: added cache flush and barriers.

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This commit is contained in:
pca006132 2020-07-14 10:53:35 +08:00
parent 49d93e20dd
commit 8e3574080c
1 changed files with 10 additions and 1 deletions
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11
src/runtime/src/kernel/core1.rs
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@ -5,7 +5,12 @@ use alloc::borrow::ToOwned;
use log::{debug, info, error};
use cslice::CSlice;
use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
use libcortex_a9::{
enable_fpu,
cache::{dcci_slice, iciallu, bpiall},
asm::{dsb, isb},
sync_channel
};
use dyld::{self, Library};
use crate::eh_artiq;
use super::{
@ -92,7 +97,11 @@ impl KernelImage {
// Flush data cache entries for the image in DDR, including
// Memory/Instruction Synchronization Barriers
dcci_slice(self.library.image.data);
dsb();
iciallu();
bpiall();
dsb();
isb();
(mem::transmute::<u32, fn()>(self.__modinit__))();