diff --git a/src/gateware/si549.py b/src/gateware/si549.py
index d98a327..3ae8948 100644
--- a/src/gateware/si549.py
+++ b/src/gateware/si549.py
@@ -150,11 +150,9 @@ class ADPLLProgrammer(Module):
         fsm = FSM()
         self.submodules += fsm
 
-        adpll = Signal.like(self.adpll)
-
         fsm.act("IDLE",
             If(self.stb,
-                NextValue(adpll, self.adpll),
+                NextValue(self.nack, 0),
                 NextState("START")
             )
         )
@@ -174,47 +172,47 @@ class ADPLLProgrammer(Module):
                 If(master.ack,
                     NextState("DATA0")
                 ).Else(
-                    self.nack.eq(1),
+                    NextValue(self.nack, 1),
                     NextState("STOP")
                 )
             )
         )
         fsm.act("DATA0",
-            master.data.eq(adpll[0:8]),
+            master.data.eq(self.adpll[0:8]),
             master.write.eq(1),
             If(master.ready,
                 If(master.ack,
                     NextState("DATA1")
                 ).Else(
-                    self.nack.eq(1),
+                    NextValue(self.nack, 1),
                     NextState("STOP")
                 )
             )
         )
         fsm.act("DATA1",
-            master.data.eq(adpll[8:16]),
+            master.data.eq(self.adpll[8:16]),
             master.write.eq(1),
             If(master.ready,
                 If(master.ack,
                     NextState("DATA2")
                 ).Else(
-                    self.nack.eq(1),
+                    NextValue(self.nack, 1),
                     NextState("STOP")
                 )
             )
         )
         fsm.act("DATA2",
-            master.data.eq(adpll[16:24]),
+            master.data.eq(self.adpll[16:24]),
             master.write.eq(1),
             If(master.ready,
-                If(~master.ack, self.nack.eq(1)),
+                If(~master.ack, NextValue(self.nack, 1)),
                 NextState("STOP")
             )
         )
         fsm.act("STOP",
             master.stop.eq(1),
             If(master.ready,
-                If(~master.ack, self.nack.eq(1)),
+                If(~master.ack, NextValue(self.nack, 1)),
                 NextState("IDLE")
             )
         )
@@ -228,7 +226,7 @@ class Si549(Module, AutoCSR):
         self.i2c_address = CSRStorage(7)
 
         self.adpll = CSRStorage(24)
-        self.adpll_stb = CSRStorage()
+        self.adpll_stb = CSR()
         self.adpll_busy = CSRStatus()
         self.nack = CSRStatus()
 
@@ -244,11 +242,12 @@ class Si549(Module, AutoCSR):
 
         self.submodules.programmer = ADPLLProgrammer()
 
+        self.sync += self.programmer.stb.eq(self.adpll_stb.re)
+
         self.comb += [
             self.programmer.i2c_divider.eq(self.i2c_divider.storage),
             self.programmer.i2c_address.eq(self.i2c_address.storage),
             self.programmer.adpll.eq(self.adpll.storage),
-            self.programmer.stb.eq(self.adpll_stb.storage),
             self.adpll_busy.status.eq(self.programmer.busy),
             self.nack.status.eq(self.programmer.nack)
         ]