M-Labs/artiq-zynq
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gateware: add extra ident info, source version

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This commit is contained in:
mwojcik 2024-12-05 14:22:38 +08:00
parent e1f493f3ca
commit 8713d25301
5 changed files with 47 additions and 9 deletions
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4
flake.nix
View File

@ -11,6 +11,7 @@
zynqpkgs = zynq-rs.packages.x86_64-linux;
artiqpkgs = artiq.packages.x86_64-linux;
llvmPackages_11 = zynq-rs.llvmPackages_11;
zynqRev = self.sourceInfo.rev or "unknown";
rust = zynq-rs.rust;
rustPlatform = zynq-rs.rustPlatform;
@ -137,6 +138,7 @@
llvmPackages_11.clang-unwrapped
];
buildPhase = ''
export VERSIONEER_ZYNQ_REV=${zynqRev}
export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
export CARGO_HOME=$(mktemp -d cargo-home.XXX)
@ -164,6 +166,7 @@
];
}
''
export VERSIONEER_ZYNQ_REV=${zynqRev}
python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
mkdir -p $out $out/nix-support
cp build/top.bit $out
@ -386,6 +389,7 @@
binutils-arm
pre-commit
];
VERSIONEER_ZYNQ_REV="${zynqRev}";
XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
ZYNQ_RS = "${zynq-rs}";

4
src/gateware/config.py
View File

@ -1,5 +1,9 @@
import os
from misoc.integration import cpu_interface
def get_zynq_rev():
return os.getenv("VERSIONEER_ZYNQ_REV", default="unknown")
def write_csr_file(soc, filename):
with open(filename, "w") as f:
f.write(cpu_interface.get_csr_rust(

6
src/gateware/ebaz4205.py
View File

@ -125,7 +125,11 @@ class EBAZ4205(SoCCore):
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
)
ident = self.__class__.__name__
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
self.__class__.__name__
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

21
src/gateware/kasli_soc.py
View File

@ -21,13 +21,14 @@ from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import *
from artiq.gateware.wrpll import wrpll
from artiq._version import get_version
import dma
import analyzer
import acpki
import drtio_aux_controller
import zynq_clocking
from config import write_csr_file, write_mem_file, write_rustc_cfg_file
from config import get_zynq_rev, write_csr_file, write_mem_file, write_rustc_cfg_file
eem_iostandard_dict = {
0: "LVDS_25",
@ -115,7 +116,11 @@ class GenericStandalone(SoCCore):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
ident = description["variant"]
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
description["variant"]
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -229,7 +234,11 @@ class GenericMaster(SoCCore):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
ident = description["variant"]
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
description["variant"]
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -438,7 +447,11 @@ class GenericSatellite(SoCCore):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
ident = description["variant"]
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
description["variant"]
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)

21
src/gateware/zc706.py
View File

@ -19,13 +19,14 @@ from artiq.gateware.drtio.transceiver import gtx_7series
from artiq.gateware.drtio.siphaser import SiPhaser7Series
from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
from artiq.gateware.drtio import *
from artiq._version import get_version
import dma
import analyzer
import acpki
import drtio_aux_controller
import zynq_clocking
from config import write_csr_file, write_mem_file, write_rustc_cfg_file
from config import get_zynq_rev, write_csr_file, write_mem_file, write_rustc_cfg_file
class SMAClkinForward(Module):
def __init__(self, platform):
@ -130,7 +131,11 @@ class ZC706(SoCCore):
platform = zc706.Platform()
prepare_zc706_platform(platform)
ident = self.__class__.__name__
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
self.__class__.__name__
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -203,7 +208,11 @@ class _MasterBase(SoCCore):
platform = zc706.Platform()
prepare_zc706_platform(platform)
ident = self.__class__.__name__
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
self.__class__.__name__
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -344,7 +353,11 @@ class _SatelliteBase(SoCCore):
platform = zc706.Platform()
prepare_zc706_platform(platform)
ident = self.__class__.__name__
ident = "{};{};{}".format(
get_version(),
get_zynq_rev()[:8],
self.__class__.__name__,
)
if self.acpki:
ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)