rtio_clocking: init drtio first
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aa0760e4ab
commit
83d530d8ac
@ -182,11 +182,13 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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txout_buf = Signal()
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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gtx0 = self.drtio_transceiver.gtxs[0]
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self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.ps7,
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self.platform,
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txout_buf)
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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self.csr_devices.append("sys_crg")
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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# another hack since ps7 itself does not have cd_sys anymore
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# another hack since ps7 itself does not have cd_sys anymore
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@ -314,11 +316,13 @@ class GenericSatellite(SoCCore):
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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txout_buf = Signal()
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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gtx0 = self.drtio_transceiver.gtxs[0]
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self.specials += Instance("BUFG", i_I=self.drtio_transceiver.gtxs[0].txoutclk, o_O=txout_buf)
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform,
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.ps7,
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self.platform,
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txout_buf)
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self.ps7,
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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self.csr_devices.append("sys_crg")
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self.csr_devices.append("sys_crg")
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self.crg.cd_sys = self.sys_crg.cd_sys
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self.crg.cd_sys = self.sys_crg.cd_sys
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@ -199,14 +199,13 @@ class _MasterBase(SoCCore):
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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txout_buf = Signal()
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txout_buf = Signal()
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self.specials += Instance(
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gtx0 = self.drtio_transceiver.gtxs[0]
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"BUFG",
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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i_I=self.drtio_transceiver.gtxs[0].txoutclk,
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o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.platform,
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self.ps7,
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self.ps7,
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txout_buf)
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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self.csr_devices.append("sys_crg")
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self.csr_devices.append("sys_crg")
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drtio_csr_group = []
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drtio_csr_group = []
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@ -252,7 +251,6 @@ class _MasterBase(SoCCore):
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# Constrain TX & RX timing for the first transceiver channel
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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gtx0.txoutclk, gtx0.rxoutclk)
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# Constrain RX timing for the each transceiver channel
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@ -334,14 +332,16 @@ class _SatelliteBase(SoCCore):
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txout_buf = Signal()
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txout_buf = Signal()
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txout_buf.attr.add("keep")
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txout_buf.attr.add("keep")
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gtx0 = self.drtio_transceiver.gtxs[0]
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self.specials += Instance(
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self.specials += Instance(
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"BUFG",
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"BUFG",
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i_I=self.drtio_transceiver.gtxs[0].txoutclk,
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i_I=gtx0.txoutclk,
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o_O=txout_buf)
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o_O=txout_buf)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.platform,
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self.ps7,
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self.ps7,
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txout_buf)
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txout_buf,
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clk_sw=gtx0.tx_init.done)
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self.csr_devices.append("sys_crg")
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self.csr_devices.append("sys_crg")
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drtioaux_csr_group = []
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drtioaux_csr_group = []
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@ -411,7 +411,6 @@ class _SatelliteBase(SoCCore):
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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# Constrain TX & RX timing for the first transceiver channel
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# (First channel acts as master for phase alignment for all channels' TX)
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# (First channel acts as master for phase alignment for all channels' TX)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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gtx0.txoutclk, gtx0.rxoutclk)
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gtx0.txoutclk, gtx0.rxoutclk)
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# Constrain RX timing for the each transceiver channel
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# Constrain RX timing for the each transceiver channel
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@ -57,13 +57,15 @@ class ClockSwitchFSM(Module):
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NextValue(o_switch, 1),
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NextValue(o_switch, 1),
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NextValue(delay_counter, delay_counter-1),
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NextValue(delay_counter, delay_counter-1),
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If(delay_counter == 0,
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If(delay_counter == 0,
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NextState("START"))
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NextState("END"))
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)
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)
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fsm.act("END",
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NextValue(o_switch, 1),
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reset.eq(0))
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class SYSCRG(Module, AutoCSR):
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class SYSCRG(Module, AutoCSR):
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def __init__(self, platform, ps7, main_clk):
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def __init__(self, platform, ps7, main_clk, clk_sw=None):
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self.clock_switch = CSRStorage()
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self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
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self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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@ -79,10 +81,15 @@ class SYSCRG(Module, AutoCSR):
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self.submodules.clk_sw_fsm = ClockSwitchFSM()
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self.submodules.clk_sw_fsm = ClockSwitchFSM()
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage)
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if clk_sw is None:
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self.clock_switch = CSRStorage()
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage)
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else:
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self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
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self.specials += [
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self.specials += [
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Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk),
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Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_bootstrap.clk),
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# Instance("BUFG", i_I=ps7.fclk.clk[0], o_O=self.cd_sys.clk),
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Instance("PLLE2_ADV",
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_BANDWIDTH="HIGH",
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@ -106,6 +113,6 @@ class SYSCRG(Module, AutoCSR):
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]),
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AsyncResetSynchronizer(self.cd_sys, ~ps7.fclk.reset_n[0]),
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]
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]
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platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)
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platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)
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@ -66,13 +66,12 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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res
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res
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}
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}
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#[cfg(not(has_drtio))]
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fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
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fn init_rtio(timer: &mut GlobalTimer) {
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info!("Switching SYS clocks...");
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info!("Switching SYS clocks...");
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unsafe {
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unsafe {
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pl::csr::sys_crg::clock_switch_write(1);
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pl::csr::sys_crg::clock_switch_write(1);
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}
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}
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timer.delay_ms(10);
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// if it's not locked, it will hang at the CSR.
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// if it's not locked, it will hang at the CSR.
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unsafe {
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::rtio_core::reset_phy_write(1);
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@ -87,8 +86,10 @@ fn init_drtio(timer: &mut GlobalTimer)
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unsafe {
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unsafe {
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pl::csr::drtio_transceiver::stable_clkin_write(1);
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pl::csr::drtio_transceiver::stable_clkin_write(1);
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}
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}
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timer.delay_ms(2); // wait for CPLL/QPLL lock
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timer.delay_ms(20); // wait for CPLL/QPLL/MMCM lock
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unsafe {
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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}
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}
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@ -228,8 +229,9 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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}
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}
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}
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}
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init_rtio(timer, clk);
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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init_drtio(timer);
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init_drtio(timer);
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#[cfg(not(has_drtio))]
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init_rtio(timer);
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}
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}
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@ -390,25 +390,6 @@ fn drtiosat_process_errors() {
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}
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}
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}
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}
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#[cfg(has_rtio_crg)]
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fn init_rtio_crg(timer: &mut GlobalTimer) {
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unsafe {
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csr::rtio_crg::pll_reset_write(0);
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}
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timer.delay_us(150);
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let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
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if !locked {
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error!("RTIO clock failed");
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}
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else {
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info!("RTIO PLL locked");
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}
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}
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#[cfg(not(has_rtio_crg))]
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fn init_rtio_crg(_timer: &mut GlobalTimer) { }
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fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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let now = timer.get_time();
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let now = timer.get_time();
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let mut ts_ms = Milliseconds(*ts);
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let mut ts_ms = Milliseconds(*ts);
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@ -472,22 +453,15 @@ pub extern fn main_core0() -> i32 {
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#[cfg(has_si5324)]
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#[cfg(has_si5324)]
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si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
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si5324::setup(&mut i2c, &SI5324_SETTINGS, si5324::Input::Ckin1, &mut timer).expect("cannot initialize Si5324");
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info!("Switching SYS clocks...");
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unsafe {
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unsafe {
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csr::drtio_transceiver::stable_clkin_write(1);
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csr::drtio_transceiver::stable_clkin_write(1);
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}
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}
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timer.delay_us(1500); // wait for CPLL/QPLL lock
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timer.delay_us(20_000); // wait for CPLL/QPLL/MMCM lock
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info!("Switching SYS clocks...");
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unsafe {
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csr::sys_crg::clock_switch_write(1);
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}
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timer.delay_us(10_000); // wait for SYS PLL lock
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unsafe {
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
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}
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}
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init_rtio_crg(&mut timer);
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#[cfg(has_drtio_routing)]
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#[cfg(has_drtio_routing)]
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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let mut repeaters = [repeater::Repeater::default(); csr::DRTIOREP.len()];
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