rustfmt
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136e24f597
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src
@ -1,10 +1,11 @@
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use crate::pl;
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::timer::GlobalTimer;
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use libconfig::Config;
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use libsupport_zynq::alloc::format;
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use log::{debug, error, info};
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use crate::pl;
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struct SerdesConfig {
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pub delay: [u8; 4],
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}
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@ -61,11 +62,7 @@ unsafe fn assign_delay(timer: &mut GlobalTimer) -> SerdesConfig {
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if prev_low_rate <= curr_low_rate && curr_low_rate >= 0.5 {
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let prev_dev = 0.5 - prev_low_rate;
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let curr_dev = curr_low_rate - 0.5;
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let selected_idx = if prev_dev < curr_dev {
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curr_dly - 1
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} else {
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curr_dly
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};
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let selected_idx = if prev_dev < curr_dev { curr_dly - 1 } else { curr_dly };
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// The setup setup/hold calibration timing (even with
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// tolerance) might be invalid in other lanes due to skew.
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@ -110,11 +107,7 @@ unsafe fn assign_delay(timer: &mut GlobalTimer) -> SerdesConfig {
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let index = (best_dly as isize + dly_delta) as u8;
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let low_rate = read_align(index, timer);
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// abs() from f32 is not available in core library
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let deviation = if low_rate < 0.5 {
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0.5 - low_rate
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} else {
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low_rate - 0.5
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};
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let deviation = if low_rate < 0.5 { 0.5 - low_rate } else { low_rate - 0.5 };
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if deviation < min_deviation {
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min_deviation = deviation;
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@ -128,9 +121,7 @@ unsafe fn assign_delay(timer: &mut GlobalTimer) -> SerdesConfig {
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debug!("setup/hold timing calibration: {:?}", delay_list);
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SerdesConfig {
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delay: delay_list,
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}
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SerdesConfig { delay: delay_list }
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}
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fn read_align(dly: u8, timer: &mut GlobalTimer) -> f32 {
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@ -219,7 +210,11 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
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info!("storing calibration timing values into sd card");
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}
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Err(e) => {
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error!("calibration successful but calibration timing values cannot be stored into sd card. Error:{}", e);
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error!(
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"calibration successful but calibration timing values cannot be stored into sd card. \
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Error:{}",
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e
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);
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}
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};
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}
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@ -29,10 +29,10 @@ pub mod mem;
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#[rustfmt::skip]
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#[path = "../../../build/pl.rs"]
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pub mod pl;
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#[cfg(has_si5324)]
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pub mod si5324;
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#[cfg(has_drtio_eem)]
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pub mod drtio_eem;
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#[cfg(has_si5324)]
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pub mod si5324;
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use core::{cmp, str};
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@ -13,11 +13,11 @@ use core::cell::RefCell;
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use ksupport;
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use libasync::task;
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#[cfg(has_drtio_eem)]
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use libboard_artiq::drtio_eem;
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#[cfg(feature = "target_kasli_soc")]
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use libboard_artiq::io_expander;
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use libboard_artiq::{identifier_read, logger, pl};
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#[cfg(has_drtio_eem)]
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use libboard_artiq::drtio_eem;
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use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
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use libconfig::Config;
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use libcortex_a9::l2c::enable_l2_cache;
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