diff --git a/default.nix b/default.nix
index baee912..1edc3fb 100644
--- a/default.nix
+++ b/default.nix
@@ -88,13 +88,13 @@ let
     # FSBL startup
     fsbl-sd = pkgs.runCommand "zc706-${variant}-fsbl-sd"
       {
-        buildInputs = [ mkbootimage ];
+        buildInputs = [ mkbootimage zc706-fsbl];
       }
       ''
       # TODO: use self-built fsbl
       bifdir=`mktemp -d`
       cd $bifdir
-      ln -s ${./fsbl.elf} fsbl.elf
+      ln -s ${zc706-fsbl}/fsbl.elf fsbl.elf
       ln -s ${gateware}/top.bit top.bit
       ln -s ${firmware}/runtime.elf runtime.elf
       cat > boot.bif << EOF
diff --git a/fsbl.elf b/fsbl.elf
deleted file mode 100644
index e57257d..0000000
Binary files a/fsbl.elf and /dev/null differ
diff --git a/fsbl.nix b/fsbl.nix
index 06397af..2acd272 100644
--- a/fsbl.nix
+++ b/fsbl.nix
@@ -10,6 +10,7 @@ pkgs.stdenv.mkDerivation {
     rev = "65c849ed46c88c67457e1fc742744f96db968ff1";
     sha256 = "1rvl06ha40dzd6s9aa4sylmksh4xb9dqaxq462lffv1fdk342pda";
   };
+  patches = [ ./fsbl.patch ];
   nativeBuildInputs = [
     pkgs.gnumake
     gnutoolchain.binutils
@@ -17,13 +18,14 @@ pkgs.stdenv.mkDerivation {
   ];
   patchPhase =
     ''
+    patch -p1 -i ${./fsbl.patch}
     patchShebangs lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh
     echo 'SEARCH_DIR("${gnutoolchain.newlib}/arm-none-eabi/lib");' >> lib/sw_apps/zynq_fsbl/src/lscript.ld
     '';
   buildPhase =
     ''
     cd lib/sw_apps/zynq_fsbl/src
-    make BOARD=${board}
+    make BOARD=${board} "CFLAGS=-DFSBL_DEBUG_INFO -g"
     '';
   installPhase = 
     ''
diff --git a/fsbl.patch b/fsbl.patch
new file mode 100644
index 0000000..f8ff379
--- /dev/null
+++ b/fsbl.patch
@@ -0,0 +1,4087 @@
+From c6ade110bdfd4ca8dc3fed1730afdba8239160d5 Mon Sep 17 00:00:00 2001
+From: pca006132 <john.lck40@gmail.com>
+Date: Wed, 17 Jun 2020 14:34:11 +0800
+Subject: [PATCH] mysterious changes...
+
+---
+ lib/sw_apps/zynq_fsbl/src/ps7_init.c | 2491 ++++++++++++--------------
+ lib/sw_apps/zynq_fsbl/src/ps7_init.h |   20 +-
+ 2 files changed, 1168 insertions(+), 1343 deletions(-)
+
+diff --git a/lib/sw_apps/zynq_fsbl/src/ps7_init.c b/lib/sw_apps/zynq_fsbl/src/ps7_init.c
+index 4f03bfb795..92851d2415 100644
+--- a/lib/sw_apps/zynq_fsbl/src/ps7_init.c
++++ b/lib/sw_apps/zynq_fsbl/src/ps7_init.c
+@@ -1,24 +1,21 @@
+ /******************************************************************************
+ *
+-* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
+-* 
+-* Permission is hereby granted, free of charge, to any person obtaining a copy
+-* of this software and associated documentation files (the "Software"), to deal 
+-* in the Software without restriction, including without limitation the rights 
+-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell  
+-* copies of the Software, and to permit persons to whom the Software is 
+-* furnished to do so, subject to the following conditions:
++* (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved.
+ *
+-* The above copyright notice and this permission notice shall be included in 
+-* all copies or substantial portions of the Software.
++* Permission is hereby granted, free of charge, to any person obtaining a copy of this
++* software and associated documentation files (the "Software"), to deal in the Software
++* without restriction, including without limitation the rights to use, copy, modify, merge,
++* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
++* persons to whom the Software is furnished to do so, subject to the following conditions:
+ *
+-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+-* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-* THE SOFTWARE.
++* The above copyright notice and this permission notice shall be included in all copies or
++* substantial portions of the Software.
++*
++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
++* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ *
+@@ -40,8 +37,8 @@ unsigned long ps7_pll_init_data_3_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: PLL SLCR REGISTERS
+     // .. .. START: ARM PLL INIT
+@@ -251,8 +248,8 @@ unsigned long ps7_pll_init_data_3_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -267,21 +264,21 @@ unsigned long ps7_clock_init_data_3_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: CLOCK CONTROL SLCR REGISTERS
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000128[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. DIVISOR0 = 0x23
+-    // .. ==> 0XF8000128[13:8] = 0x00000023U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF8000128[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // ..
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000138[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -343,96 +340,34 @@ unsigned long ps7_clock_init_data_3_0[] = {
+     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+     // .. 
+     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+-    // .. CLKACT0 = 0x1
+-    // .. ==> 0XF800015C[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. CLKACT1 = 0x0
+-    // .. ==> 0XF800015C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF800015C[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0xe
+-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF800015C[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+-    // .. CAN0_MUX = 0x0
+-    // .. ==> 0XF8000160[5:0] = 0x00000000U
+-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+-    // .. CAN0_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[6:6] = 0x00000000U
+-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+-    // .. CAN1_MUX = 0x0
+-    // .. ==> 0XF8000160[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+-    // .. CAN1_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[22:22] = 0x00000000U
+-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+-    // .. CLKACT = 0x1
+-    // .. ==> 0XF8000168[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000168[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR = 0x5
+-    // .. ==> 0XF8000168[13:8] = 0x00000005U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+-    // .. 
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. ..
+     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000170[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000170[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000170[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000180[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000180[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000180[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000190[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000190[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000190[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+-    // .. CLK_621_TRUE = 0x1
+-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. 
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x4
++    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
++    // .. ..
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. ..
+     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+     // .. DMA_CPU_2XCLKACT = 0x1
+     // .. ==> 0XF800012C[0:0] = 0x00000001U
+@@ -461,9 +396,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
+     // .. SPI1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[15:15] = 0x00000000U
+     // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+-    // .. CAN0_CPU_1XCLKACT = 0x1
+-    // .. ==> 0XF800012C[16:16] = 0x00000001U
+-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. CAN0_CPU_1XCLKACT = 0x0
++    // .. ==> 0XF800012C[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+     // .. CAN1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[17:17] = 0x00000000U
+     // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+@@ -489,7 +424,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
+     // .. ==> 0XF800012C[24:24] = 0x00000001U
+     // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+     // .. START: THIS SHOULD BE BLANK
+     // .. FINISH: THIS SHOULD BE BLANK
+@@ -497,8 +432,8 @@ unsigned long ps7_clock_init_data_3_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -538,17 +473,17 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+     // .. .. FINISH: LOCK DDR
+-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
++    // .. .. ==> 0XF8006004[11:0] = 0x00000082U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000082U
+     // .. .. reserved_reg_ddrc_active_ranks = 0x1
+     // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+     // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+     // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+     // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+     // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001082U),
+     // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+     // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+     // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+@@ -593,15 +528,15 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+-    // .. .. reg_ddrc_wr2pre = 0x12
+-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
++    // .. .. reg_ddrc_wr2pre = 0x13
++    // .. .. ==> 0XF8006018[4:0] = 0x00000013U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000013U
+     // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+     // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+-    // .. .. reg_ddrc_t_faw = 0x10
+-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
++    // .. .. reg_ddrc_t_faw = 0x11
++    // .. .. ==> 0XF8006018[15:10] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004400U
+     // .. .. reg_ddrc_t_ras_max = 0x24
+     // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+     // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+@@ -611,37 +546,37 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. reg_ddrc_t_cke = 0x4
+     // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452444D3U),
+     // .. .. reg_ddrc_write_latency = 0x5
+     // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+     // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+     // .. .. reg_ddrc_rd2wr = 0x7
+     // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+-    // .. .. reg_ddrc_wr2rd = 0xe
+-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+-    // .. .. reg_ddrc_t_xp = 0x4
+-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_wr2rd = 0xf
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003C00U
++    // .. .. reg_ddrc_t_xp = 0x5
++    // .. .. ==> 0XF800601C[19:15] = 0x00000005U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00028000U
+     // .. .. reg_ddrc_pad_pd = 0x0
+     // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+     // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+-    // .. .. reg_ddrc_rd2pre = 0x4
+-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_rd2pre = 0x5
++    // .. .. ==> 0XF800601C[27:23] = 0x00000005U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02800000U
+     // .. .. reg_ddrc_t_rcd = 0x7
+     // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
++    // .. ..
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+     // .. .. reg_ddrc_t_ccd = 0x4
+     // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+-    // .. .. reg_ddrc_t_rrd = 0x4
+-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. .. reg_ddrc_t_rrd = 0x5
++    // .. .. ==> 0XF8006020[7:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
+     // .. .. reg_ddrc_refresh_margin = 0x2
+     // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+@@ -666,8 +601,8 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. reg_ddrc_dis_pad_pd = 0x0
+     // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+     // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872B0U),
+     // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+     // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -713,20 +648,20 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+-    // .. .. reg_ddrc_mr = 0x930
+-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
++    // .. .. reg_ddrc_mr = 0xb30
++    // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000B30U
+     // .. .. reg_ddrc_emr = 0x4
+     // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+     // .. .. reg_ddrc_burst_rdwr = 0x4
+     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+     // .. .. reg_ddrc_post_cke_x1024 = 0x1
+     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+@@ -734,7 +669,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+     // .. .. reg_ddrc_force_low_pri_n = 0x0
+     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -818,8 +753,14 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. reg_phy_idle_local_odt = 0x3
+     // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+     // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
++    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
++    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
++    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
++    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
++    // .. ..
++    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+     // .. .. reg_phy_rd_cmd_to_data = 0x0
+     // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+@@ -1030,16 +971,6 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+-    // .. .. START: RESET ECC ERROR
+-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+-    // .. .. FINISH: RESET ECC ERROR
+     // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+     // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -1177,38 +1108,38 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+     // .. .. reg_phy_gatelvl_init_ratio = 0xee
+-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
++    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+     // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x25
++    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
++    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x19
++    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
++    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
++    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
++    // .. .. reg_phy_gatelvl_init_ratio = 0x109
++    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+     // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+     // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+     // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+@@ -1253,9 +1184,9 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1263,10 +1194,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1274,10 +1205,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
++    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1285,10 +1216,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
++    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1296,10 +1227,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
++    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -1307,10 +1238,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
++    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -1318,10 +1249,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
++    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -1329,10 +1260,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
++    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -1340,10 +1271,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xde
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1351,10 +1282,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1362,10 +1293,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
++    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1373,10 +1304,10 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xea
++    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -1384,7 +1315,7 @@ unsigned long ps7_ddr_init_data_3_0[] = {
+     // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+     // .. .. reg_phy_bl2 = 0x0
+     // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+@@ -1669,8 +1600,8 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: OCM REMAPPING
+     // .. VREF_EN = 0x1
+@@ -1981,9 +1912,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. REFIO_EN = 0x1
+     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+-    // .. reserved_REFIO_TEST = 0x3
+-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
++    // .. reserved_REFIO_TEST = 0x0
++    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+     // .. reserved_REFIO_PULLUP_EN = 0x0
+     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+@@ -1994,7 +1925,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
++    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+     // .. .. START: ASSERT RESET
+     // .. .. RESET = 1
+     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+@@ -2070,9 +2001,21 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+     // .. FINISH: DDRIOB SETTINGS
+     // .. START: MIO PROGRAMMING
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF8000700[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000700[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF8000700[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -2086,7 +2029,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000700[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000704[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -2322,9 +2265,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000724[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000724[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000724[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000724[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -2347,13 +2290,13 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000724[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000728[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000728[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000728[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000728[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -2376,13 +2319,13 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000728[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF800072C[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF800072C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800072C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF800072C[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -2405,13 +2348,13 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF800072C[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000730[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000730[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000730[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000730[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -2434,13 +2377,13 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000730[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000734[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000734[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000734[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000734[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -2463,22 +2406,10 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000734[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+-    // .. TRI_ENABLE = 0
+-    // .. ==> 0XF8000738[0:0] = 0x00000000U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000738[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. L1_SEL = 0
+-    // .. ==> 0XF8000738[2:2] = 0x00000000U
+-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+-    // .. L2_SEL = 0
+-    // .. ==> 0XF8000738[4:3] = 0x00000000U
+-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 0
+-    // .. ==> 0XF8000738[7:5] = 0x00000000U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000738[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+     // .. Speed = 0
+     // .. ==> 0XF8000738[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -2492,7 +2423,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF8000738[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+     // .. TRI_ENABLE = 1
+     // .. ==> 0XF800073C[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -3380,9 +3311,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+     EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+     // .. L0_SEL = 0
+     // .. ==> 0XF80007B8[1:1] = 0x00000000U
+     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+@@ -3392,9 +3323,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007B8[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007B8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007B8[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -3408,7 +3339,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF80007B8[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007BC[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -3421,9 +3352,9 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007BC[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007BC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007BC[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -3437,7 +3368,7 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. ==> 0XF80007BC[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007C0[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -3615,18 +3546,18 @@ unsigned long ps7_mio_init_data_3_0[] = {
+     // .. SDIO0_WP_SEL = 15
+     // .. ==> 0XF8000830[5:0] = 0x0000000FU
+     // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+-    // .. SDIO0_CD_SEL = 0
+-    // .. ==> 0XF8000830[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
++    // .. SDIO0_CD_SEL = 14
++    // .. ==> 0XF8000830[21:16] = 0x0000000EU
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+     // .. FINISH: MIO PROGRAMMING
+     // .. START: LOCK IT BACK
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -3641,8 +3572,8 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+     // .. IBUF_DISABLE_MODE = 0x1
+@@ -3682,13 +3613,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // .. START: SRAM/NOR SET OPMODE
+     // .. FINISH: SRAM/NOR SET OPMODE
+-    // .. START: TRACE CURRENT PORT SIZE
+-    // .. FINISH: TRACE CURRENT PORT SIZE
+     // .. START: UART REGISTERS
+     // .. BDIV = 0x6
+     // .. ==> 0XE0001034[7:0] = 0x00000006U
+@@ -3781,12 +3710,13 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     // .. .. START: NOR CS1 BASE ADDRESS
+     // .. .. FINISH: NOR CS1 BASE ADDRESS
+     // .. .. START: USB RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x80
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: DIR MODE BANK 0
+     // .. .. .. START: DIR MODE BANK 1
+     // .. .. .. FINISH: DIR MODE BANK 1
+@@ -3807,11 +3737,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
++    // .. .. .. OP_ENABLE_0 = 0x80
++    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
++    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+     // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+@@ -3824,154 +3754,158 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
+-    // .. .. .. 
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xff7f
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+-    // .. .. .. DATA_0_LSW = 0x80
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+-    // .. .. .. 
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. ..
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
+     // .. .. FINISH: USB RESET
+     // .. .. START: ENET RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE BANK 0
+-    // .. .. .. START: DIR MODE BANK 1
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
+     // .. .. FINISH: ENET RESET
+     // .. .. START: I2C RESET
+-    // .. .. .. START: DIR MODE GPIO BANK0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE GPIO BANK0
+-    // .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE GPIO BANK1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: OUTPUT ENABLE
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+@@ -3980,22 +3914,31 @@ unsigned long ps7_peripherals_init_data_3_0[] = {
+     EMIT_MASKDELAY(0XF8F00200, 1),
+     // .. .. .. FINISH: ADD 1 MS DELAY
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
+     // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
+     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+     // FINISH: top
+     //
+@@ -4010,8 +3953,8 @@ unsigned long ps7_post_config_3_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: ENABLING LEVEL SHIFTER
+     // .. USER_LVL_INP_EN_0 = 1
+@@ -4105,13 +4048,15 @@ unsigned long ps7_post_config_3_0[] = {
+     // .. .. FINISH: AFI2 REGISTERS
+     // .. .. START: AFI3 REGISTERS
+     // .. .. FINISH: AFI3 REGISTERS
++    // .. .. START: AFI2 SECURE REGISTER
++    // .. .. FINISH: AFI2 SECURE REGISTER
+     // .. FINISH: AFI REGISTERS
+     // .. START: LOCK IT BACK
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -4127,18 +4072,18 @@ unsigned long ps7_debug_3_0[] = {
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+     // .. .. FINISH: UNLOCKING CTI REGISTERS
+     // .. .. START: ENABLING CTI MODULES AND CHANNELS
+     // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+@@ -4158,8 +4103,8 @@ unsigned long ps7_pll_init_data_2_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: PLL SLCR REGISTERS
+     // .. .. START: ARM PLL INIT
+@@ -4369,8 +4314,8 @@ unsigned long ps7_pll_init_data_2_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -4385,21 +4330,21 @@ unsigned long ps7_clock_init_data_2_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: CLOCK CONTROL SLCR REGISTERS
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000128[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. DIVISOR0 = 0x23
+-    // .. ==> 0XF8000128[13:8] = 0x00000023U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF8000128[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // ..
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000138[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -4461,96 +4406,34 @@ unsigned long ps7_clock_init_data_2_0[] = {
+     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+     // .. 
+     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+-    // .. CLKACT0 = 0x1
+-    // .. ==> 0XF800015C[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. CLKACT1 = 0x0
+-    // .. ==> 0XF800015C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF800015C[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0xe
+-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF800015C[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+-    // .. CAN0_MUX = 0x0
+-    // .. ==> 0XF8000160[5:0] = 0x00000000U
+-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+-    // .. CAN0_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[6:6] = 0x00000000U
+-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+-    // .. CAN1_MUX = 0x0
+-    // .. ==> 0XF8000160[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+-    // .. CAN1_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[22:22] = 0x00000000U
+-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+-    // .. CLKACT = 0x1
+-    // .. ==> 0XF8000168[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000168[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR = 0x5
+-    // .. ==> 0XF8000168[13:8] = 0x00000005U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+-    // .. 
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. ..
+     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000170[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000170[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000170[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000180[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000180[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000180[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000190[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000190[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000190[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+-    // .. CLK_621_TRUE = 0x1
+-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. 
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x4
++    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
++    // .. ..
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. ..
+     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+     // .. DMA_CPU_2XCLKACT = 0x1
+     // .. ==> 0XF800012C[0:0] = 0x00000001U
+@@ -4579,9 +4462,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
+     // .. SPI1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[15:15] = 0x00000000U
+     // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+-    // .. CAN0_CPU_1XCLKACT = 0x1
+-    // .. ==> 0XF800012C[16:16] = 0x00000001U
+-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. CAN0_CPU_1XCLKACT = 0x0
++    // .. ==> 0XF800012C[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+     // .. CAN1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[17:17] = 0x00000000U
+     // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+@@ -4607,7 +4490,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
+     // .. ==> 0XF800012C[24:24] = 0x00000001U
+     // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+     // .. START: THIS SHOULD BE BLANK
+     // .. FINISH: THIS SHOULD BE BLANK
+@@ -4615,8 +4498,8 @@ unsigned long ps7_clock_init_data_2_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -4656,9 +4539,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+     // .. .. FINISH: LOCK DDR
+-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
++    // .. .. ==> 0XF8006004[11:0] = 0x00000082U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000082U
+     // .. .. reg_ddrc_active_ranks = 0x1
+     // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+     // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+@@ -4680,8 +4563,8 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+     // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+     // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+     // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+     // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+@@ -4726,15 +4609,15 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+-    // .. .. reg_ddrc_wr2pre = 0x12
+-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
++    // .. .. reg_ddrc_wr2pre = 0x13
++    // .. .. ==> 0XF8006018[4:0] = 0x00000013U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000013U
+     // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+     // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+-    // .. .. reg_ddrc_t_faw = 0x10
+-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
++    // .. .. reg_ddrc_t_faw = 0x11
++    // .. .. ==> 0XF8006018[15:10] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004400U
+     // .. .. reg_ddrc_t_ras_max = 0x24
+     // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+     // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+@@ -4744,37 +4627,37 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. reg_ddrc_t_cke = 0x4
+     // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452444D3U),
+     // .. .. reg_ddrc_write_latency = 0x5
+     // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+     // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+     // .. .. reg_ddrc_rd2wr = 0x7
+     // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+-    // .. .. reg_ddrc_wr2rd = 0xe
+-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+-    // .. .. reg_ddrc_t_xp = 0x4
+-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_wr2rd = 0xf
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003C00U
++    // .. .. reg_ddrc_t_xp = 0x5
++    // .. .. ==> 0XF800601C[19:15] = 0x00000005U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00028000U
+     // .. .. reg_ddrc_pad_pd = 0x0
+     // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+     // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+-    // .. .. reg_ddrc_rd2pre = 0x4
+-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_rd2pre = 0x5
++    // .. .. ==> 0XF800601C[27:23] = 0x00000005U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02800000U
+     // .. .. reg_ddrc_t_rcd = 0x7
+     // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
++    // .. ..
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+     // .. .. reg_ddrc_t_ccd = 0x4
+     // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+-    // .. .. reg_ddrc_t_rrd = 0x4
+-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. .. reg_ddrc_t_rrd = 0x5
++    // .. .. ==> 0XF8006020[7:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
+     // .. .. reg_ddrc_refresh_margin = 0x2
+     // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+@@ -4805,8 +4688,8 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. reg_ddrc_loopback = 0x0
+     // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+     // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
+     // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+     // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -4855,20 +4738,20 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+-    // .. .. reg_ddrc_mr = 0x930
+-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
++    // .. .. reg_ddrc_mr = 0xb30
++    // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000B30U
+     // .. .. reg_ddrc_emr = 0x4
+     // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+     // .. .. reg_ddrc_burst_rdwr = 0x4
+     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+     // .. .. reg_ddrc_post_cke_x1024 = 0x1
+     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+@@ -4876,7 +4759,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+     // .. .. reg_ddrc_force_low_pri_n = 0x0
+     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -5228,16 +5111,6 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+-    // .. .. START: RESET ECC ERROR
+-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+-    // .. .. FINISH: RESET ECC ERROR
+     // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+     // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -5426,38 +5299,38 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+     // .. .. reg_phy_gatelvl_init_ratio = 0xee
+-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
++    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+     // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x25
++    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
++    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x19
++    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
++    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
++    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
++    // .. .. reg_phy_gatelvl_init_ratio = 0x109
++    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+     // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+     // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+     // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+@@ -5502,9 +5375,9 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5512,10 +5385,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5523,10 +5396,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
++    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5534,10 +5407,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
++    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5545,10 +5418,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
++    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -5556,10 +5429,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
++    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -5567,10 +5440,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
++    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -5578,10 +5451,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
++    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -5589,10 +5462,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xde
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5600,10 +5473,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5611,10 +5484,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
++    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5622,10 +5495,10 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xea
++    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -5633,7 +5506,7 @@ unsigned long ps7_ddr_init_data_2_0[] = {
+     // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+     // .. .. reg_phy_loopback = 0x0
+     // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -5945,8 +5818,8 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: OCM REMAPPING
+     // .. VREF_EN = 0x1
+@@ -6263,9 +6136,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. REFIO_EN = 0x1
+     // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+     // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+-    // .. REFIO_TEST = 0x3
+-    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+-    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
++    // .. REFIO_TEST = 0x0
++    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
++    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+     // .. REFIO_PULLUP_EN = 0x0
+     // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+     // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+@@ -6276,7 +6149,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+     // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
++    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+     // .. .. START: ASSERT RESET
+     // .. .. RESET = 1
+     // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+@@ -6355,11 +6228,23 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+     // .. FINISH: DDRIOB SETTINGS
+     // .. START: MIO PROGRAMMING
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF8000700[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. Speed = 0
+-    // .. ==> 0XF8000700[8:8] = 0x00000000U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000700[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    // .. Speed = 0
++    // .. ==> 0XF8000700[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+     // .. IO_Type = 1
+     // .. ==> 0XF8000700[11:9] = 0x00000001U
+@@ -6371,7 +6256,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000700[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000704[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -6607,9 +6492,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000724[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000724[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000724[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000724[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -6632,13 +6517,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000724[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000728[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000728[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000728[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000728[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -6661,13 +6546,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000728[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF800072C[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF800072C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800072C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF800072C[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -6690,13 +6575,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF800072C[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000730[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000730[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000730[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000730[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -6719,13 +6604,13 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000730[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000734[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000734[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000734[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000734[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -6748,22 +6633,10 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000734[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+-    // .. TRI_ENABLE = 0
+-    // .. ==> 0XF8000738[0:0] = 0x00000000U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000738[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. L1_SEL = 0
+-    // .. ==> 0XF8000738[2:2] = 0x00000000U
+-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+-    // .. L2_SEL = 0
+-    // .. ==> 0XF8000738[4:3] = 0x00000000U
+-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 0
+-    // .. ==> 0XF8000738[7:5] = 0x00000000U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000738[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+     // .. Speed = 0
+     // .. ==> 0XF8000738[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -6777,7 +6650,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF8000738[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+     // .. TRI_ENABLE = 1
+     // .. ==> 0XF800073C[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -7665,9 +7538,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+     EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+     // .. L0_SEL = 0
+     // .. ==> 0XF80007B8[1:1] = 0x00000000U
+     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+@@ -7677,9 +7550,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007B8[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007B8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007B8[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -7693,7 +7566,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF80007B8[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007BC[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -7706,9 +7579,9 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007BC[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007BC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007BC[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -7722,7 +7595,7 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. ==> 0XF80007BC[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007C0[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -7900,18 +7773,18 @@ unsigned long ps7_mio_init_data_2_0[] = {
+     // .. SDIO0_WP_SEL = 15
+     // .. ==> 0XF8000830[5:0] = 0x0000000FU
+     // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+-    // .. SDIO0_CD_SEL = 0
+-    // .. ==> 0XF8000830[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
++    // .. SDIO0_CD_SEL = 14
++    // .. ==> 0XF8000830[21:16] = 0x0000000EU
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+     // .. FINISH: MIO PROGRAMMING
+     // .. START: LOCK IT BACK
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -7926,8 +7799,8 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+     // .. IBUF_DISABLE_MODE = 0x1
+@@ -7967,13 +7840,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // .. START: SRAM/NOR SET OPMODE
+     // .. FINISH: SRAM/NOR SET OPMODE
+-    // .. START: TRACE CURRENT PORT SIZE
+-    // .. FINISH: TRACE CURRENT PORT SIZE
+     // .. START: UART REGISTERS
+     // .. BDIV = 0x6
+     // .. ==> 0XE0001034[7:0] = 0x00000006U
+@@ -8072,12 +7943,13 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     // .. .. START: NOR CS1 BASE ADDRESS
+     // .. .. FINISH: NOR CS1 BASE ADDRESS
+     // .. .. START: USB RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x80
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: DIR MODE BANK 0
+     // .. .. .. START: DIR MODE BANK 1
+     // .. .. .. FINISH: DIR MODE BANK 1
+@@ -8098,11 +7970,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
++    // .. .. .. OP_ENABLE_0 = 0x80
++    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
++    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+     // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+@@ -8115,154 +7987,158 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
+-    // .. .. .. 
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xff7f
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+-    // .. .. .. DATA_0_LSW = 0x80
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+-    // .. .. .. 
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. ..
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
+     // .. .. FINISH: USB RESET
+     // .. .. START: ENET RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE BANK 0
+-    // .. .. .. START: DIR MODE BANK 1
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
+     // .. .. FINISH: ENET RESET
+     // .. .. START: I2C RESET
+-    // .. .. .. START: DIR MODE GPIO BANK0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE GPIO BANK0
+-    // .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE GPIO BANK1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: OUTPUT ENABLE
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+@@ -8271,22 +8147,31 @@ unsigned long ps7_peripherals_init_data_2_0[] = {
+     EMIT_MASKDELAY(0XF8F00200, 1),
+     // .. .. .. FINISH: ADD 1 MS DELAY
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
+     // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
+     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+     // FINISH: top
+     //
+@@ -8301,8 +8186,8 @@ unsigned long ps7_post_config_2_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: ENABLING LEVEL SHIFTER
+     // .. USER_INP_ICT_EN_0 = 3
+@@ -8395,8 +8280,8 @@ unsigned long ps7_post_config_2_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -8412,18 +8297,18 @@ unsigned long ps7_debug_2_0[] = {
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+     // .. .. FINISH: UNLOCKING CTI REGISTERS
+     // .. .. START: ENABLING CTI MODULES AND CHANNELS
+     // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+@@ -8443,8 +8328,8 @@ unsigned long ps7_pll_init_data_1_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: PLL SLCR REGISTERS
+     // .. .. START: ARM PLL INIT
+@@ -8654,8 +8539,8 @@ unsigned long ps7_pll_init_data_1_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -8670,21 +8555,21 @@ unsigned long ps7_clock_init_data_1_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: CLOCK CONTROL SLCR REGISTERS
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000128[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. DIVISOR0 = 0x23
+-    // .. ==> 0XF8000128[13:8] = 0x00000023U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF8000128[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
++    // .. DIVISOR0 = 0xf
++    // .. ==> 0XF8000128[13:8] = 0x0000000FU
++    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000F00U
++    // .. DIVISOR1 = 0x7
++    // .. ==> 0XF8000128[25:20] = 0x00000007U
++    // ..     ==> MASK : 0x03F00000U    VAL : 0x00700000U
++    // ..
++    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U),
+     // .. CLKACT = 0x1
+     // .. ==> 0XF8000138[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -8746,96 +8631,34 @@ unsigned long ps7_clock_init_data_1_0[] = {
+     // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+     // .. 
+     EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+-    // .. CLKACT0 = 0x1
+-    // .. ==> 0XF800015C[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. CLKACT1 = 0x0
+-    // .. ==> 0XF800015C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF800015C[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0xe
+-    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+-    // .. DIVISOR1 = 0x3
+-    // .. ==> 0XF800015C[25:20] = 0x00000003U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+-    // .. CAN0_MUX = 0x0
+-    // .. ==> 0XF8000160[5:0] = 0x00000000U
+-    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+-    // .. CAN0_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[6:6] = 0x00000000U
+-    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+-    // .. CAN1_MUX = 0x0
+-    // .. ==> 0XF8000160[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+-    // .. CAN1_REF_SEL = 0x0
+-    // .. ==> 0XF8000160[22:22] = 0x00000000U
+-    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+-    // .. CLKACT = 0x1
+-    // .. ==> 0XF8000168[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000168[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR = 0x5
+-    // .. ==> 0XF8000168[13:8] = 0x00000005U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+-    // .. 
++    // .. .. START: TRACE CLOCK
++    // .. .. FINISH: TRACE CLOCK
++    // .. .. CLKACT = 0x1
++    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR = 0x5
++    // .. .. ==> 0XF8000168[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. ..
+     EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000170[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000170[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000170[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000180[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000180[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000180[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF8000190[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF8000190[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF8000190[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+-    // .. SRCSEL = 0x0
+-    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+-    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+-    // .. DIVISOR0 = 0x14
+-    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+-    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+-    // .. DIVISOR1 = 0x1
+-    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+-    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+-    // .. 
+-    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+-    // .. CLK_621_TRUE = 0x1
+-    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. 
++    // .. .. SRCSEL = 0x0
++    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
++    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
++    // .. .. DIVISOR0 = 0x5
++    // .. .. ==> 0XF8000170[13:8] = 0x00000005U
++    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
++    // .. .. DIVISOR1 = 0x4
++    // .. .. ==> 0XF8000170[25:20] = 0x00000004U
++    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
++    // .. ..
++    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U),
++    // .. .. CLK_621_TRUE = 0x1
++    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
++    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. ..
+     EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+     // .. DMA_CPU_2XCLKACT = 0x1
+     // .. ==> 0XF800012C[0:0] = 0x00000001U
+@@ -8864,9 +8687,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
+     // .. SPI1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[15:15] = 0x00000000U
+     // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+-    // .. CAN0_CPU_1XCLKACT = 0x1
+-    // .. ==> 0XF800012C[16:16] = 0x00000001U
+-    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
++    // .. CAN0_CPU_1XCLKACT = 0x0
++    // .. ==> 0XF800012C[16:16] = 0x00000000U
++    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+     // .. CAN1_CPU_1XCLKACT = 0x0
+     // .. ==> 0XF800012C[17:17] = 0x00000000U
+     // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+@@ -8892,7 +8715,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
+     // .. ==> 0XF800012C[24:24] = 0x00000001U
+     // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
++    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC044DU),
+     // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+     // .. START: THIS SHOULD BE BLANK
+     // .. FINISH: THIS SHOULD BE BLANK
+@@ -8900,8 +8723,8 @@ unsigned long ps7_clock_init_data_1_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -8941,9 +8764,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+     // .. .. FINISH: LOCK DDR
+-    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+-    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+-    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
++    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x82
++    // .. .. ==> 0XF8006004[11:0] = 0x00000082U
++    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000082U
+     // .. .. reg_ddrc_active_ranks = 0x1
+     // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+     // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+@@ -8965,8 +8788,8 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+     // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081082U),
+     // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+     // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+     // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+@@ -9011,15 +8834,15 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+-    // .. .. reg_ddrc_wr2pre = 0x12
+-    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
++    // .. .. reg_ddrc_wr2pre = 0x13
++    // .. .. ==> 0XF8006018[4:0] = 0x00000013U
++    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000013U
+     // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+     // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+-    // .. .. reg_ddrc_t_faw = 0x10
+-    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+-    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
++    // .. .. reg_ddrc_t_faw = 0x11
++    // .. .. ==> 0XF8006018[15:10] = 0x00000011U
++    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004400U
+     // .. .. reg_ddrc_t_ras_max = 0x24
+     // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+     // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+@@ -9029,37 +8852,37 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. reg_ddrc_t_cke = 0x4
+     // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452444D3U),
+     // .. .. reg_ddrc_write_latency = 0x5
+     // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+     // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+     // .. .. reg_ddrc_rd2wr = 0x7
+     // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+     // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+-    // .. .. reg_ddrc_wr2rd = 0xe
+-    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+-    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+-    // .. .. reg_ddrc_t_xp = 0x4
+-    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
++    // .. .. reg_ddrc_wr2rd = 0xf
++    // .. .. ==> 0XF800601C[14:10] = 0x0000000FU
++    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003C00U
++    // .. .. reg_ddrc_t_xp = 0x5
++    // .. .. ==> 0XF800601C[19:15] = 0x00000005U
++    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00028000U
+     // .. .. reg_ddrc_pad_pd = 0x0
+     // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+     // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+-    // .. .. reg_ddrc_rd2pre = 0x4
+-    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+-    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
++    // .. .. reg_ddrc_rd2pre = 0x5
++    // .. .. ==> 0XF800601C[27:23] = 0x00000005U
++    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02800000U
+     // .. .. reg_ddrc_t_rcd = 0x7
+     // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+     // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
++    // .. ..
++    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x7282BCE5U),
+     // .. .. reg_ddrc_t_ccd = 0x4
+     // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+-    // .. .. reg_ddrc_t_rrd = 0x4
+-    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+-    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
++    // .. .. reg_ddrc_t_rrd = 0x5
++    // .. .. ==> 0XF8006020[7:5] = 0x00000005U
++    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000A0U
+     // .. .. reg_ddrc_refresh_margin = 0x2
+     // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+     // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+@@ -9090,8 +8913,8 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. reg_ddrc_loopback = 0x0
+     // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+     // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
+     // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+     // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -9140,20 +8963,20 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+-    // .. .. reg_ddrc_mr = 0x930
+-    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+-    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
++    // .. .. reg_ddrc_mr = 0xb30
++    // .. .. ==> 0XF8006030[15:0] = 0x00000B30U
++    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000B30U
+     // .. .. reg_ddrc_emr = 0x4
+     // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+     // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
++    // .. ..
++    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040B30U),
+     // .. .. reg_ddrc_burst_rdwr = 0x4
+     // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+     // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+-    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+-    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+-    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
++    // .. .. reg_ddrc_pre_cke_x1024 = 0x16d
++    // .. .. ==> 0XF8006034[13:4] = 0x0000016DU
++    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x000016D0U
+     // .. .. reg_ddrc_post_cke_x1024 = 0x1
+     // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+     // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+@@ -9161,7 +8984,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+     // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
++    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U),
+     // .. .. reg_ddrc_force_low_pri_n = 0x0
+     // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -9476,16 +9299,6 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+-    // .. .. START: RESET ECC ERROR
+-    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+-    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+-    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+-    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+-    // .. .. FINISH: RESET ECC ERROR
+     // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+     // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -9647,38 +9460,38 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+-    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+-    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+-    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+-    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+-    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+-    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+-    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+-    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+-    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+-    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
++    // .. .. reg_phy_wrlvl_init_ratio = 0x1e
++    // .. .. ==> 0XF800612C[9:0] = 0x0000001EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001EU
+     // .. .. reg_phy_gatelvl_init_ratio = 0xee
+-    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
++    // .. .. ==> 0XF800612C[19:10] = 0x000000EEU
+     // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
++    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003B81EU),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x25
++    // .. .. ==> 0XF8006130[9:0] = 0x00000025U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000025U
++    // .. .. reg_phy_gatelvl_init_ratio = 0x10d
++    // .. .. ==> 0XF8006130[19:10] = 0x0000010DU
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00043400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00043425U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x19
++    // .. .. ==> 0XF8006134[9:0] = 0x00000019U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000019U
++    // .. .. reg_phy_gatelvl_init_ratio = 0xf3
++    // .. .. ==> 0XF8006134[19:10] = 0x000000F3U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003CC00U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003CC19U),
++    // .. .. reg_phy_wrlvl_init_ratio = 0x2a
++    // .. .. ==> 0XF8006138[9:0] = 0x0000002AU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000002AU
++    // .. .. reg_phy_gatelvl_init_ratio = 0x109
++    // .. .. ==> 0XF8006138[19:10] = 0x00000109U
++    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00042400U
++    // .. .. 
++    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0004242AU),
+     // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+     // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+     // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+@@ -9723,9 +9536,9 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+     EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+-    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9e
++    // .. .. ==> 0XF8006154[9:0] = 0x0000009EU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009EU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9733,10 +9546,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+-    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
++    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009EU),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa5
++    // .. .. ==> 0XF8006158[9:0] = 0x000000A5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A5U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9744,10 +9557,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+-    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
++    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x000000A5U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0x99
++    // .. .. ==> 0XF800615C[9:0] = 0x00000099U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000099U
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9755,10 +9568,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+-    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+-    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
++    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000099U),
++    // .. .. reg_phy_wr_dqs_slave_ratio = 0xaa
++    // .. .. ==> 0XF8006160[9:0] = 0x000000AAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000AAU
+     // .. .. reg_phy_wr_dqs_slave_force = 0x0
+     // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9766,10 +9579,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+-    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
++    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000AAU),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
++    // .. .. ==> 0XF8006168[10:0] = 0x00000143U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -9777,10 +9590,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+-    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
++    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000143U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x162
++    // .. .. ==> 0XF800616C[10:0] = 0x00000162U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000162U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -9788,10 +9601,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+-    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
++    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x00000162U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x148
++    // .. .. ==> 0XF8006170[10:0] = 0x00000148U
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000148U
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -9799,10 +9612,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+-    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+-    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+-    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
++    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000148U),
++    // .. .. reg_phy_fifo_we_slave_ratio = 0x15e
++    // .. .. ==> 0XF8006174[10:0] = 0x0000015EU
++    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000015EU
+     // .. .. reg_phy_fifo_we_in_force = 0x0
+     // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+@@ -9810,10 +9623,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+     // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+-    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
++    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x0000015EU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xde
++    // .. .. ==> 0XF800617C[9:0] = 0x000000DEU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DEU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9821,10 +9634,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+-    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
++    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DEU),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xe5
++    // .. .. ==> 0XF8006180[9:0] = 0x000000E5U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E5U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9832,10 +9645,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+-    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
++    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000E5U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xd9
++    // .. .. ==> 0XF8006184[9:0] = 0x000000D9U
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D9U
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9843,10 +9656,10 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+-    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+-    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+-    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
++    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000D9U),
++    // .. .. reg_phy_wr_data_slave_ratio = 0xea
++    // .. .. ==> 0XF8006188[9:0] = 0x000000EAU
++    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000EAU
+     // .. .. reg_phy_wr_data_slave_force = 0x0
+     // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+@@ -9854,7 +9667,7 @@ unsigned long ps7_ddr_init_data_1_0[] = {
+     // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+     // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+     // .. .. 
+-    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
++    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000EAU),
+     // .. .. reg_phy_loopback = 0x0
+     // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+     // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -10166,8 +9979,8 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: OCM REMAPPING
+     // .. VREF_EN = 0x1
+@@ -10573,9 +10386,21 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+     // .. FINISH: DDRIOB SETTINGS
+     // .. START: MIO PROGRAMMING
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF8000700[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF8000700[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000700[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
++    // .. L1_SEL = 0
++    // .. ==> 0XF8000700[2:2] = 0x00000000U
++    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
++    // .. L2_SEL = 0
++    // .. ==> 0XF8000700[4:3] = 0x00000000U
++    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
++    // .. L3_SEL = 0
++    // .. ==> 0XF8000700[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF8000700[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -10589,7 +10414,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000700[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
++    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000704[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -10825,9 +10650,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000724[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000724[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000724[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000724[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -10850,13 +10675,13 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000724[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000728[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000728[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000728[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000728[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -10879,13 +10704,13 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000728[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF800072C[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF800072C[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF800072C[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF800072C[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -10908,13 +10733,13 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF800072C[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000730[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000730[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000730[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000730[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -10937,13 +10762,13 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000730[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001202U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF8000734[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000734[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
++    // .. L0_SEL = 1
++    // .. ==> 0XF8000734[1:1] = 0x00000001U
++    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+     // .. L1_SEL = 0
+     // .. ==> 0XF8000734[2:2] = 0x00000000U
+     // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+@@ -10966,22 +10791,10 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000734[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+-    // .. TRI_ENABLE = 0
+-    // .. ==> 0XF8000738[0:0] = 0x00000000U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+-    // .. L0_SEL = 0
+-    // .. ==> 0XF8000738[1:1] = 0x00000000U
+-    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+-    // .. L1_SEL = 0
+-    // .. ==> 0XF8000738[2:2] = 0x00000000U
+-    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+-    // .. L2_SEL = 0
+-    // .. ==> 0XF8000738[4:3] = 0x00000000U
+-    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 0
+-    // .. ==> 0XF8000738[7:5] = 0x00000000U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
++    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001202U),
++    // .. TRI_ENABLE = 1
++    // .. ==> 0XF8000738[0:0] = 0x00000001U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+     // .. Speed = 0
+     // .. ==> 0XF8000738[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -10995,7 +10808,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF8000738[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
++    EMIT_MASKWRITE(0XF8000738, 0x00003F01U ,0x00001201U),
+     // .. TRI_ENABLE = 1
+     // .. ==> 0XF800073C[0:0] = 0x00000001U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+@@ -11883,9 +11696,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+     EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+-    // .. TRI_ENABLE = 1
+-    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+-    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
++    // .. TRI_ENABLE = 0
++    // .. ==> 0XF80007B8[0:0] = 0x00000000U
++    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+     // .. L0_SEL = 0
+     // .. ==> 0XF80007B8[1:1] = 0x00000000U
+     // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+@@ -11895,9 +11708,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007B8[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007B8[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007B8[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -11911,7 +11724,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF80007B8[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
++    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007BC[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -11924,9 +11737,9 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. L2_SEL = 0
+     // .. ==> 0XF80007BC[4:3] = 0x00000000U
+     // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+-    // .. L3_SEL = 1
+-    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+-    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
++    // .. L3_SEL = 0
++    // .. ==> 0XF80007BC[7:5] = 0x00000000U
++    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+     // .. Speed = 0
+     // .. ==> 0XF80007BC[8:8] = 0x00000000U
+     // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+@@ -11940,7 +11753,7 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. ==> 0XF80007BC[13:13] = 0x00000000U
+     // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+     // .. 
+-    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
++    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001200U),
+     // .. TRI_ENABLE = 0
+     // .. ==> 0XF80007C0[0:0] = 0x00000000U
+     // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+@@ -12118,18 +11931,18 @@ unsigned long ps7_mio_init_data_1_0[] = {
+     // .. SDIO0_WP_SEL = 15
+     // .. ==> 0XF8000830[5:0] = 0x0000000FU
+     // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+-    // .. SDIO0_CD_SEL = 0
+-    // .. ==> 0XF8000830[21:16] = 0x00000000U
+-    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
++    // .. SDIO0_CD_SEL = 14
++    // .. ==> 0XF8000830[21:16] = 0x0000000EU
++    // ..     ==> MASK : 0x003F0000U    VAL : 0x000E0000U
+     // .. 
+-    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
++    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x000E000FU),
+     // .. FINISH: MIO PROGRAMMING
+     // .. START: LOCK IT BACK
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -12144,8 +11957,8 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+     // .. IBUF_DISABLE_MODE = 0x1
+@@ -12185,13 +11998,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // .. START: SRAM/NOR SET OPMODE
+     // .. FINISH: SRAM/NOR SET OPMODE
+-    // .. START: TRACE CURRENT PORT SIZE
+-    // .. FINISH: TRACE CURRENT PORT SIZE
+     // .. START: UART REGISTERS
+     // .. BDIV = 0x6
+     // .. ==> 0XE0001034[7:0] = 0x00000006U
+@@ -12290,12 +12101,13 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     // .. .. START: NOR CS1 BASE ADDRESS
+     // .. .. FINISH: NOR CS1 BASE ADDRESS
+     // .. .. START: USB RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
++    // .. .. .. START: USB0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. DIRECTION_0 = 0x80
++    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: DIR MODE BANK 0
+     // .. .. .. START: DIR MODE BANK 1
+     // .. .. .. FINISH: DIR MODE BANK 1
+@@ -12316,11 +12128,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
++    // .. .. .. OP_ENABLE_0 = 0x80
++    // .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
++    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+     // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
++    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+@@ -12333,154 +12145,158 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
+-    // .. .. .. 
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xff7f
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+-    // .. .. .. DATA_0_LSW = 0x80
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+-    // .. .. .. 
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. MASK_0_LSW = 0xff7f
++    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
++    // .. .. .. .. DATA_0_LSW = 0x80
++    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
++    // .. .. .. ..
+     EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: USB0 RESET
+     // .. .. FINISH: USB RESET
+     // .. .. START: ENET RESET
+-    // .. .. .. START: DIR MODE BANK 0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE BANK 0
+-    // .. .. .. START: DIR MODE BANK 1
++    // .. .. .. START: ENET0 RESET
++    // .. .. .. .. START: DIR MODE BANK 0
++    // .. .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. .. START: DIR MODE BANK 1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE BANK 0
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+     // .. .. .. START: OUTPUT ENABLE BANK 1
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+-    // .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+     // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF0000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
++    // .. .. .. .. START: ADD 1 MS DELAY
++    // .. .. .. ..
+     EMIT_MASKDELAY(0XF8F00200, 1),
+-    // .. .. .. FINISH: ADD 1 MS DELAY
+-    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xf7ff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+-    // .. .. .. DATA_0_LSW = 0x800
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+-    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+-    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: ADD 1 MS DELAY
++    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
++    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. MASK_1_LSW = 0x7fff
++    // .. .. .. .. ==> 0XE000A008[31:16] = 0x00007FFFU
++    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x7FFF0000U
++    // .. .. .. .. DATA_1_LSW = 0x8000
++    // .. .. .. .. ==> 0XE000A008[15:0] = 0x00008000U
++    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00008000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0x7FFF8000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: ENET0 RESET
+     // .. .. FINISH: ENET RESET
+     // .. .. START: I2C RESET
+-    // .. .. .. START: DIR MODE GPIO BANK0
+-    // .. .. .. DIRECTION_0 = 0x2880
+-    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+-    // .. .. .. FINISH: DIR MODE GPIO BANK0
+-    // .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. START: I2C0 RESET
++    // .. .. .. .. START: DIR MODE GPIO BANK0
++    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
++    // .. .. .. .. START: DIR MODE GPIO BANK1
++    // .. .. .. .. DIRECTION_1 = 0xc000
++    // .. .. .. .. ==> 0XE000A244[21:0] = 0x0000C000U
++    // .. .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. ..
++    EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: DIR MODE GPIO BANK1
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+     // .. .. .. START: OUTPUT ENABLE
+-    // .. .. .. OP_ENABLE_0 = 0x2880
+-    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+-    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: OUTPUT ENABLE
++    // .. .. .. OP_ENABLE_1 = 0xc000
++    // .. .. .. ==> 0XE000A248[21:0] = 0x0000C000U
++    // .. .. ..     ==> MASK : 0x003FFFFFU    VAL : 0x0000C000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU ,0x0000C000U),
+     // .. .. .. FINISH: OUTPUT ENABLE
+     // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x0
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x0
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00000000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF0000U),
+     // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+     // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+     // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+@@ -12489,22 +12305,31 @@ unsigned long ps7_peripherals_init_data_1_0[] = {
+     EMIT_MASKDELAY(0XF8F00200, 1),
+     // .. .. .. FINISH: ADD 1 MS DELAY
+     // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+-    // .. .. .. MASK_0_LSW = 0xdfff
+-    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+-    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+-    // .. .. .. DATA_0_LSW = 0x2000
+-    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+-    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+-    // .. .. .. 
+-    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+     // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+     // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+     // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+-    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+-    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. MASK_1_LSW = 0xbfff
++    // .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU
++    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xBFFF0000U
++    // .. .. .. DATA_1_LSW = 0x4000
++    // .. .. .. ==> 0XE000A008[15:0] = 0x00004000U
++    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00004000U
++    // .. .. .. 
++    EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU ,0xBFFF4000U),
++    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
++    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
++    // .. .. .. FINISH: I2C0 RESET
+     // .. .. FINISH: I2C RESET
++    // .. .. START: NOR CHIP SELECT
++    // .. .. .. START: DIR MODE BANK 0
++    // .. .. .. FINISH: DIR MODE BANK 0
++    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
++    // .. .. .. START: OUTPUT ENABLE BANK 0
++    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
++    // .. .. FINISH: NOR CHIP SELECT
+     // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+     // FINISH: top
+     //
+@@ -12519,8 +12344,8 @@ unsigned long ps7_post_config_1_0[] = {
+     // .. UNLOCK_KEY = 0XDF0D
+     // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
++    // ..
++    EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+     // .. FINISH: SLCR SETTINGS
+     // .. START: ENABLING LEVEL SHIFTER
+     // .. USER_INP_ICT_EN_0 = 3
+@@ -12613,8 +12438,8 @@ unsigned long ps7_post_config_1_0[] = {
+     // .. LOCK_KEY = 0X767B
+     // .. ==> 0XF8000004[15:0] = 0x0000767BU
+     // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+-    // .. 
+-    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
++    // ..
++    EMIT_WRITE(0XF8000004, 0x0000767BU),
+     // .. FINISH: LOCK IT BACK
+     // FINISH: top
+     //
+@@ -12630,18 +12455,18 @@ unsigned long ps7_debug_1_0[] = {
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
+     // .. .. KEY = 0XC5ACCE55
+     // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+     // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+-    // .. .. 
+-    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
++    // .. ..
++    EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
+     // .. .. FINISH: UNLOCKING CTI REGISTERS
+     // .. .. START: ENABLING CTI MODULES AND CHANNELS
+     // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+@@ -12686,7 +12511,7 @@ ps7GetSiliconVersion () {
+ }
+ 
+ void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+-        unsigned long *addr = (unsigned long*) add;
++        volatile unsigned long *addr = (volatile unsigned long*) add;
+         *addr = ( val & mask ) | ( *addr & ~mask);
+         //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+ }
+@@ -12706,7 +12531,7 @@ int mask_poll(unsigned long add , unsigned long mask ) {
+ }
+ 
+ unsigned long mask_read(unsigned long add , unsigned long mask ) {
+-        unsigned long *addr = (unsigned long*) add;
++        volatile unsigned long *addr = (volatile unsigned long*) add;
+         unsigned long val = (*addr & mask);
+         //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+         return val;
+diff --git a/lib/sw_apps/zynq_fsbl/src/ps7_init.h b/lib/sw_apps/zynq_fsbl/src/ps7_init.h
+index 40db14df12..641e3469dc 100644
+--- a/lib/sw_apps/zynq_fsbl/src/ps7_init.h
++++ b/lib/sw_apps/zynq_fsbl/src/ps7_init.h
+@@ -1,7 +1,7 @@
+ /******************************************************************************
+ *
+-* Copyright (C) 2012 - 2014 Xilinx, Inc.  All rights reserved.
+-* 
++* Copyright (C) 2018 Xilinx, Inc.  All rights reserved.
++*
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal 
+ * in the Software without restriction, including without limitation the rights 
+@@ -12,9 +12,9 @@
+ * The above copyright notice and this permission notice shall be included in 
+ * all copies or substantial portions of the Software.
+ *
+-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
+-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+@@ -89,7 +89,7 @@ extern unsigned long  * ps7_peripherals_init_data;
+ 
+ #define APU_FREQ  666666687
+ #define DDR_FREQ  533333374
+-#define DCI_FREQ  10158731
++#define DCI_FREQ  10158730
+ #define QSPI_FREQ  200000000
+ #define SMC_FREQ  10000000
+ #define ENET0_FREQ  25000000
+@@ -102,13 +102,13 @@ extern unsigned long  * ps7_peripherals_init_data;
+ #define I2C_FREQ  111111115
+ #define WDT_FREQ  111111115
+ #define TTC_FREQ  50000000
+-#define CAN_FREQ  23809523
++#define CAN_FREQ  10000000
+ #define PCAP_FREQ  200000000
+ #define TPIU_FREQ  200000000
+ #define FPGA0_FREQ  50000000
+-#define FPGA1_FREQ  50000000
+-#define FPGA2_FREQ  50000000
+-#define FPGA3_FREQ  50000000
++#define FPGA1_FREQ  10000000
++#define FPGA2_FREQ  10000000
++#define FPGA3_FREQ  10000000
+ 
+ 
+ /* For delay calculation using global registers*/
+-- 
+2.25.4
+