M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

gateware: updated gtx interface

Browse Source
This commit is contained in:
mwojcik 2021-08-10 15:11:21 +02:00
parent 118893c0b2
commit 7ff59f57a9
2 changed files with 10 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/gateware/kasli_soc.py
View File

@ -207,20 +207,11 @@ class GenericMaster(SoCCore):
# kasli_soc has no SATA, but it has 4x SFP # kasli_soc has no SATA, but it has 4x SFP
# not sure yet why sfp0 is omitted in MasterMode # not sure yet why sfp0 is omitted in MasterMode
drtio_data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
drtio_tx_pads = []
drtio_rx_pads = []
for sfp in drtio_data_pads:
drtio_tx_pads += [sfp.txp, sfp.txn]
drtio_rx_pads += [sfp.rxp, sfp.rxn]
# this does not work for now ^ GTX expects p/n subsignals in tx/rx signals,
# rather than txp/txn ... subsignals
# probably need to modify kasli_soc platform in migen
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx?
tx_pads=drtio_tx_pads, pads=data_pads,
rx_pads=drtio_rx_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
@ -346,17 +337,11 @@ class GenericSatellite(SoCCore):
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
drtio_data_pads = [platform.request("sfp", i) for i in range(4)] data_pads = [platform.request("sfp", i) for i in range(4)]
drtio_tx_pads = []
drtio_rx_pads = []
for sfp in drtio_data_pads:
drtio_tx_pads += [sfp.txp, sfp.txn]
drtio_rx_pads += [sfp.rxp, sfp.rxn]
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx? clock_pads=platform.request("clk125_gtp"), # referred to as clk gtp in schematics, but for gtx?
tx_pads=drtio_tx_pads, pads=data_pads,
rx_pads=drtio_rx_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")

20
src/gateware/zc706.py
View File

@ -275,18 +275,14 @@ class Master(ZC706):
platform = self.platform platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1) self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = [ data_pads = [
platform.request("sfp_tx") platform.request("sfp")
]
rx_pads = [
platform.request("sfp_rx")
] ]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads, pads=data_pads,
rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
@ -372,18 +368,14 @@ class Satellite(ZC706):
platform = self.platform platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1) self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = [ data_pads = [
platform.request("sfp_tx") platform.request("sfp")
]
rx_pads = [
platform.request("sfp_rx")
] ]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX( self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads, pads=data_pads,
rx_pads=rx_pads,
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")