removed references for clock, replaced with timer

src/libboard_artiqzynq/Cargo.toml

@@ -4,7 +4,7 @@ version = "0.0.0"
 authors = ["M-Labs"]
 
 [lib]
-name = "board_artiqzynq"
+name = "libboard_artiqzynq"
 
 [dependencies]
 log = "0.4"

src/libboard_artiqzynq/clock.rs

@@ -1,38 +0,0 @@
-use core::i64;
-use csr; // <- port
-
-const INIT: u64 = i64::MAX as u64;
-const FREQ: u64 = csr::CONFIG_CLOCK_FREQUENCY as u64;
-
-pub fn init() {
-    unsafe {
-        csr::timer0::en_write(0);
-        csr::timer0::load_write(INIT);
-        csr::timer0::reload_write(INIT);
-        csr::timer0::en_write(1);
-    }
-}
-
-pub fn get_us() -> u64 {
-    unsafe {
-        csr::timer0::update_value_write(1);
-        (INIT - csr::timer0::value_read()) / (FREQ / 1_000_000)
-    }
-}
-
-pub fn get_ms() -> u64 {
-    unsafe {
-        csr::timer0::update_value_write(1);
-        (INIT - csr::timer0::value_read()) / (FREQ / 1_000)
-    }
-}
-
-pub fn spin_us(interval: u64) {
-    unsafe {
-        csr::timer0::update_value_write(1);
-        let threshold = csr::timer0::value_read() - interval * (FREQ / 1_000_000);
-        while csr::timer0::value_read() > threshold {
-            csr::timer0::update_value_write(1)
-        }
-    }
-}

src/satman/jdcg.rs

@@ -1,5 +1,6 @@
 pub mod jesd {
-    use board_misoc::{csr, clock}; // <- port
+    use libboard_artiqzynq::pl::csr;
+    use libboard_zynq::timer::GlobalTimer;
 
     pub fn reset(reset: bool) {
         unsafe {
@@ -25,18 +26,18 @@ pub mod jesd {
         }
     }
 
-    pub fn prbs(dacno: u8, en: bool) {
+    pub fn prbs(dacno: u8, en: bool, timer: GlobalTimer) {
         unsafe {
             (csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
         }
-        clock::spin_us(5000);
+        timer.delay_us(5000);
     }
 
-    pub fn stpl(dacno: u8, en: bool) {
+    pub fn stpl(dacno: u8, en: bool, timer: GlobalTimer) {
         unsafe {
             (csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
         }
-        clock::spin_us(5000);
+        timer.delay_us(5000);
     }
 
     pub fn jsync(dacno: u8) -> bool {
@@ -47,8 +48,8 @@ pub mod jesd {
 }
 
 pub mod jdac {
-    use board_misoc::{csr, clock}; // <- port
-    use board_artiq::drtioaux; // <- port
+    use libboard_artiqzynq::{pl::csr, drtioaux};
+    use libboard_zynq::timer::GlobalTimer;
 
     use super::jesd;
     use super::super::jdac_common;
@@ -83,13 +84,13 @@ pub mod jdac {
         }
     }
 
-    pub fn init() -> Result<(), &'static str> {
+    pub fn init(timer: GlobalTimer) -> Result<(), &'static str> {
         for dacno in 0..csr::JDCG.len() {
             let dacno = dacno as u8;
             info!("DAC-{} initializing...", dacno);
 
             jesd::enable(dacno, true);
-            clock::spin_us(10_000);
+            timer.delay_us(10_000);
             if !jesd::phy_done(dacno) {
                 error!("JESD core PHY not done");
                 return Err("JESD core PHY not done");
@@ -109,7 +110,7 @@ pub mod jdac {
             jesd::prbs(dacno, false);
 
             basic_request(dacno, jdac_common::INIT, 0)?;
-            clock::spin_us(5000);
+            timer.delay_us(5000);
 
             if !jesd::jsync(dacno) {
                 error!("JESD core reported bad SYNC");
@@ -121,15 +122,15 @@ pub mod jdac {
         Ok(())
     }
 
-    pub fn stpl() -> Result<(), &'static str> {
+    pub fn stpl(timer: GlobalTimer) -> Result<(), &'static str> {
         for dacno in 0..csr::JDCG.len() {
             let dacno = dacno as u8;
 
             info!("Running STPL test on DAC-{}...", dacno);
 
-            jesd::stpl(dacno, true);
+            jesd::stpl(dacno, true, timer);
             basic_request(dacno, jdac_common::STPL, 0)?;
-            jesd::stpl(dacno, false);
+            jesd::stpl(dacno, false, timer);
 
             info!("  ...done STPL test");
         }

src/satman/main.rs

@@ -7,12 +7,12 @@ extern crate log;
 use core::convert::TryFrom;
 use board_misoc::{csr, irq, ident, clock, i2c}; // <- port, use libboard_zynq
 #[cfg(has_si5324)]
-use board_artiqzynq::si5324; // <- move from runtime
+use libboard_artiqzynq::si5324;
 #[cfg(has_wrpll)]
 use board_artiq::wrpll; // <- port
 use board_artiq::spi; // <- port?, use libboard_zynq (if spi available/necessary)
-use board_artiqzynq::{drtio_routing drtioaux}; // <- artiqzync
-use board_artiqzynq::logger;
+use libboard_artiqzynq::{drtio_routing drtioaux};
+use libboard_artiqzynq::logger;
 
 mod repeater;
 #[cfg(has_jdcg)]

src/satman/repeater.rs

@@ -1,6 +1,6 @@
-use board_artiq::{drtioaux, drtio_routing};
+use board_artiqzynq::{drtioaux, drtio_routing};
 #[cfg(has_drtio_routing)]
-use board_misoc::{csr, clock};
+use board_artiqzynq::{pl::csr, clock};
 
 #[cfg(has_drtio_routing)]
 fn rep_link_rx_up(repno: u8) -> bool {