M-Labs/artiq-zynq
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kernel: added core1 instruction cache flush

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pca006132 2020-07-10 17:17:52 +08:00
parent 68d27ca2ee
commit 7aec419ed6
1 changed files with 2 additions and 1 deletions
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3
src/runtime/src/kernel/core1.rs
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@ -5,7 +5,7 @@ use alloc::borrow::ToOwned;
use log::{debug, info, error}; use log::{debug, info, error};
use cslice::CSlice; use cslice::CSlice;
use libcortex_a9::{enable_fpu, cache::dcci_slice, sync_channel}; use libcortex_a9::{enable_fpu, cache::{dcci_slice, iciallu}, sync_channel};
use dyld::{self, Library}; use dyld::{self, Library};
use crate::eh_artiq; use crate::eh_artiq;
use super::{ use super::{
@ -92,6 +92,7 @@ impl KernelImage {
// Flush data cache entries for the image in DDR, including // Flush data cache entries for the image in DDR, including
// Memory/Instruction Synchronization Barriers // Memory/Instruction Synchronization Barriers
dcci_slice(self.library.image.data); dcci_slice(self.library.image.data);
iciallu();
(mem::transmute::<u32, fn()>(self.__modinit__))(); (mem::transmute::<u32, fn()>(self.__modinit__))();