parent
7f4ccc9ded
commit
7a0e09df36
10
src/Cargo.lock
generated
10
src/Cargo.lock
generated
@ -201,7 +201,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#25c6d5eeaa6243724700e975e3935a5965c09a27"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -213,7 +213,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#25c6d5eeaa6243724700e975e3935a5965c09a27"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -237,7 +237,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#25c6d5eeaa6243724700e975e3935a5965c09a27"
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dependencies = [
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"bit_field",
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"libregister",
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@ -252,7 +252,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#25c6d5eeaa6243724700e975e3935a5965c09a27"
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dependencies = [
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"bit_field",
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"vcell",
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@ -262,7 +262,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#b65606f2d02fab273645835a102048b23c3394f7"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#25c6d5eeaa6243724700e975e3935a5965c09a27"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -2,6 +2,7 @@ use libboard_zynq::{gic, mpcore, println, stdio};
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use libcortex_a9::{
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asm,
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regs::{MPIDR, SP},
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spin_lock_yield, notify_spin_lock
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};
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use libregister::{RegisterR, RegisterW};
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use core::sync::atomic::{AtomicBool, Ordering};
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@ -27,7 +28,7 @@ pub unsafe extern "C" fn IRQ() {
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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asm::sev();
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notify_spin_lock();
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main_core1();
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}
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}
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@ -41,6 +42,6 @@ pub fn restart_core1() {
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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asm::wfe();
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spin_lock_yield();
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}
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}
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