replace rustc_cfg[ ] & change write_rustc_cfg_file
onsolidate all write..file() into config.py
parent
7cdfb1b830
commit
77d4ee41e3
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@ -142,7 +142,6 @@ def prepare_zc706_platform(platform):
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class ZC706(SoCCore):
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def __init__(self, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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@ -154,7 +153,7 @@ class ZC706(SoCCore):
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg_clock_sel"] = None
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self.config["has_rtio_crg_clock_sel"] = None
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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@ -166,14 +165,14 @@ class ZC706(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -196,7 +195,6 @@ class ZC706(SoCCore):
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class _MasterBase(SoCCore):
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def __init__(self, acpki=False, drtio100mhz=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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@ -258,18 +256,18 @@ class _MasterBase(SoCCore):
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
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self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["has_drtio"] = None
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self.config["has_drtio_routing"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_as_synthesizer"] = None
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self.config["has_si5324"] = None
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self.config["si5324_as_synthesizer"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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@ -297,14 +295,14 @@ class _MasterBase(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -331,7 +329,6 @@ class _MasterBase(SoCCore):
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class _SatelliteBase(SoCCore):
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def __init__(self, acpki=False, drtio100mhz=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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@ -405,13 +402,13 @@ class _SatelliteBase(SoCCore):
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# and registered in PS interface
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# manually, because software refers to rx/tx by halves of entire memory block, not names
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["has_drtio"] = None
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self.config["has_drtio_routing"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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# Si5324 Phaser
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self.submodules.siphaser = SiPhaser7Series(
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@ -424,8 +421,8 @@ class _SatelliteBase(SoCCore):
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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self.config["has_si5324"] = None
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self.config["has_siphaser"] = None
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rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
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# Constrain TX & RX timing for the first transceiver channel
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@ -445,7 +442,7 @@ class _SatelliteBase(SoCCore):
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self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq)
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg"] = None
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self.config["has_rtio_crg"] = None
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fix_serdes_timing_path(self.platform)
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def add_rtio(self, rtio_channels):
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@ -453,14 +450,14 @@ class _SatelliteBase(SoCCore):
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self.csr_devices.append("rtio_moninj")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -669,11 +666,14 @@ def write_mem_file(soc, filename):
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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