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@ -416,6 +416,22 @@ class _SatelliteBase(SoCCore): |
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self.csr_devices.append("routing_table") |
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class _Simple_RTIO: |
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def __init__(self): |
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platform = self.platform |
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rtio_channels = [] |
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for i in range(4): |
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phy = ttl_simple.Output(platform.request("user_led", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) |
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rtio_channels.append(rtio.LogChannel()) |
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self.add_rtio(rtio_channels) |
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class _NIST_CLOCK_RTIO: |
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""" |
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NIST clock hardware, with old backplane and 11 DDS channels |
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@ -514,6 +530,22 @@ class _NIST_QC2_RTIO: |
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self.add_rtio(rtio_channels) |
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class Simple(ZC706, _Simple_RTIO): |
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def __init__(self, acpki): |
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ZC706.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class Master(_MasterBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class Satellite(_SatelliteBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_SatelliteBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): |
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def __init__(self, acpki): |
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ZC706.__init__(self, acpki) |
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@ -546,7 +578,8 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): |
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_NIST_QC2_RTIO.__init__(self) |
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, |
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VARIANTS = {cls.__name__.lower(): cls for cls in [Simple, Master, Satellite, |
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NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, |
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} |
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@ -581,9 +614,9 @@ def main(): |
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help="build Rust compiler configuration into the specified file") |
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parser.add_argument("-g", default=None, |
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help="build gateware into the specified directory") |
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parser.add_argument("-V", "--variant", default="nist_clock", |
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parser.add_argument("-V", "--variant", default="simple", |
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help="variant: " |
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"[acpki_]nist_clock/nist_qc2[_master/_satellite] " |
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"[acpki_]simple/nist_clock/nist_qc2 " |
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"(default: %(default)s)") |
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args = parser.parse_args() |
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