M-Labs/artiq-zynq
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drtio: dmb to prevent bursts

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This commit is contained in:
mwojcik 2022-03-31 12:26:51 +08:00
parent 77ca020450
commit 6d47f4ac7e
1 changed files with 4 additions and 3 deletions
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7
src/libboard_artiq/src/drtioaux.rs
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@ -3,6 +3,7 @@ use crc;
use core_io::{ErrorKind as IoErrorKind, Error as IoError}; use core_io::{ErrorKind as IoErrorKind, Error as IoError};
use io::{proto::ProtoRead, proto::ProtoWrite, Cursor}; use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
use libboard_zynq::{timer::GlobalTimer, time::Milliseconds}; use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
use libcortex_a9::asm::dmb;
use crate::mem::mem::DRTIOAUX_MEM; use crate::mem::mem::DRTIOAUX_MEM;
use crate::pl::csr::DRTIOAUX; use crate::pl::csr::DRTIOAUX;
use crate::drtioaux_proto::Error as ProtocolError; use crate::drtioaux_proto::Error as ProtocolError;
@ -62,10 +63,10 @@ pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
// and AXI burst reads/writes are not implemented yet in gateware // and AXI burst reads/writes are not implemented yet in gateware
// thus the need for a work buffer for transmitting and copying it over // thus the need for a work buffer for transmitting and copying it over
unsafe { unsafe {
for i in (0..(len/4)).step_by(2) { for i in 0..(len/4) {
//mix offsets to prevent bursts
*dst.offset(i+1) = *src.offset(i+1);
*dst.offset(i) = *src.offset(i); *dst.offset(i) = *src.offset(i);
//data memory barrier to prevent bursts
dmb();
} }
} }
} }