From 68045ce0c52777eecd40de15d419ce8901d64eb1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 8 Jul 2020 20:37:53 +0800 Subject: [PATCH] mark RTIO clock as asychronous to system clock --- src/zc706.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/zc706.py b/src/zc706.py index b7c66d5..66997b9 100755 --- a/src/zc706.py +++ b/src/zc706.py @@ -71,6 +71,10 @@ class ZC706(SoCCore): self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) self.csr_devices.append("rtio_crg") + self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) + self.platform.add_false_path_constraints( + self.ps7.cd_sys.clk, + self.rtio_crg.cd_rtio.clk) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)