KasliSoC satellite: fix serdes timing

2023-02-20 13:06:31 +08:00 · 2023-02-20 13:06:31 +08:00 · 67f3a15f46
parent dcc5cc7555
commit 67f3a15f46
1 changed files with 2 additions and 0 deletions
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -342,6 +342,8 @@ class GenericSatellite(SoCCore):
        self.crg = self.ps7 # HACK for eem_7series to find the clock
        self.crg.cd_sys = self.sys_crg.cd_sys

+        fix_serdes_timing_path(platform)
+
        self.rtio_channels = []
        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
        if has_grabber: