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@ -152,7 +152,7 @@ class ZC706(SoCCore): |
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class _MasterBase(SoCCore): |
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def __init__(self, acpki=False, use_si5324_33=False): |
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def __init__(self, acpki=False): |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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@ -163,11 +163,7 @@ class _MasterBase(SoCCore): |
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ident = "acpki_" + ident |
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) |
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") |
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") |
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if use_si5324_33: |
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platform.add_extension(si5324_fmc33) |
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platform.add_extension(si5324_fmc33) |
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self.sys_clk_freq = 125e6 |
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@ -223,10 +219,7 @@ class _MasterBase(SoCCore): |
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self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) |
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if use_si5324_33: |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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else: |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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self.csr_devices.append("si5324_rst_n") |
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self.rustc_cfg["has_si5324"] = None |
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self.rustc_cfg["si5324_as_synthesizer"] = None |
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@ -290,7 +283,7 @@ class _MasterBase(SoCCore): |
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class _SatelliteBase(SoCCore): |
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def __init__(self, acpki=False, use_si5324_33=False): |
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def __init__(self, acpki=False): |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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@ -301,8 +294,7 @@ class _SatelliteBase(SoCCore): |
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ident = "acpki_" + ident |
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) |
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if use_si5324_33: |
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platform.add_extension(si5324_fmc33) |
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platform.add_extension(si5324_fmc33) |
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self.sys_clk_freq = 125e6 |
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platform = self.platform |
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@ -372,10 +364,7 @@ class _SatelliteBase(SoCCore): |
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platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) |
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self.csr_devices.append("siphaser") |
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if use_si5324_33: |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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else: |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) |
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) |
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self.csr_devices.append("si5324_rst_n") |
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self.rustc_cfg["has_si5324"] = None |
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self.rustc_cfg["has_siphaser"] = None |
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@ -549,12 +538,12 @@ class Simple(ZC706, _Simple_RTIO): |
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class Master(_MasterBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki, use_si5324_33=False) |
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_MasterBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class Satellite(_SatelliteBase, _Simple_RTIO): |
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def __init__(self, acpki): |
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_SatelliteBase.__init__(self, acpki, use_si5324_33=False) |
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_SatelliteBase.__init__(self, acpki) |
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_Simple_RTIO.__init__(self) |
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): |
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@ -564,13 +553,13 @@ class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): |
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class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki, use_si5324_33=True) |
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_MasterBase.__init__(self, acpki) |
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_NIST_CLOCK_RTIO.__init__(self) |
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class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): |
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def __init__(self, acpki): |
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_SatelliteBase.__init__(self, acpki, use_si5324_33=True) |
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_SatelliteBase.__init__(self, acpki) |
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_NIST_CLOCK_RTIO.__init__(self) |
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class NIST_QC2(ZC706, _NIST_QC2_RTIO): |
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@ -580,12 +569,12 @@ class NIST_QC2(ZC706, _NIST_QC2_RTIO): |
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class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): |
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def __init__(self, acpki): |
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_MasterBase.__init__(self, acpki, use_si5324_33=True) |
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_MasterBase.__init__(self, acpki) |
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_NIST_QC2_RTIO.__init__(self) |
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class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): |
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def __init__(self, acpki): |
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_SatelliteBase.__init__(self, acpki, use_si5324_33=True) |
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_SatelliteBase.__init__(self, acpki) |
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_NIST_QC2_RTIO.__init__(self) |
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