M-Labs/artiq-zynq
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update configuration of IBUFDS_GTE2

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Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
This commit is contained in:
Denis Ovchinnikov 2023-05-30 12:01:02 +08:00 committed by Gitea
parent 5e6dca61a9
commit 63594d7e3d
2 changed files with 8 additions and 5 deletions
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7
src/gateware/kasli_soc.py
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@ -71,9 +71,12 @@ class GTP125BootstrapClock(Module):
platform.add_period_constraint(bootstrap_125.p, 8.0) platform.add_period_constraint(bootstrap_125.p, 8.0)
self.specials += [ self.specials += [
Instance("IBUFDS_GTE2", Instance("IBUFDS_GTE2",
p_CLKSWING_CFG="0b11",
i_CEB=0, i_CEB=0,
i_I=bootstrap_125.p, i_IB=bootstrap_125.n, o_O=bootstrap_se), i_I=bootstrap_125.p, i_IB=bootstrap_125.n,
o_O=bootstrap_se,
p_CLKCM_CFG="TRUE",
p_CLKRCV_TRST="TRUE",
p_CLKSWING_CFG=3),
Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk) Instance("BUFG", i_I=bootstrap_se, o_O=self.cd_bootstrap.clk)
] ]

6
src/gateware/zc706.py
View File

@ -149,9 +149,9 @@ class ZC706(SoCCore):
i_CEB=0, i_CEB=0,
i_I=si5324_out.p, i_IB=si5324_out.n, i_I=si5324_out.p, i_IB=si5324_out.n,
o_O=cdr_clk, o_O=cdr_clk,
p_CLKCM_CFG="0b1", p_CLKCM_CFG="TRUE",
p_CLKRCV_TRST="0b1", p_CLKRCV_TRST="TRUE",
p_CLKSWING_CFG="0b11"), p_CLKSWING_CFG=3),
Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf) Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
] ]
self.rustc_cfg["has_si5324"] = None self.rustc_cfg["has_si5324"] = None