M-Labs/artiq-zynq
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change init order, avoid providing bootstrap clock

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This commit is contained in:
mwojcik 2023-01-11 14:31:04 +08:00
parent b34f445e55
commit 5ab402139c
3 changed files with 9 additions and 14 deletions
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10
src/gateware/kasli_soc.py
View File

@ -28,7 +28,6 @@ import drtio_aux_controller
class SYSCRG(Module, AutoCSR): class SYSCRG(Module, AutoCSR):
def __init__(self, platform): def __init__(self, platform):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus() self.pll_locked = CSRStatus()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@ -51,15 +50,14 @@ class SYSCRG(Module, AutoCSR):
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
p_BANDWIDTH="HIGH", p_BANDWIDTH="HIGH",
p_REF_JITTER1=0.001, p_REF_JITTER1=0.001,
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, p_CLKIN1_PERIOD=8.0,
i_CLKIN2=clk_synth_se, i_CLKIN1=clk_synth_se,
# Warning: CLKINSEL=0 means CLKIN2 is selected i_CLKINSEL=1,
i_CLKINSEL=0,
# VCO @ 1.5GHz when using 125MHz input # VCO @ 1.5GHz when using 125MHz input
p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=fb_clk, i_CLKFBIN=fb_clk,
i_RST=self.pll_reset.storage, i_RST=0,
o_CLKFBOUT=fb_clk, o_CLKFBOUT=fb_clk,

6
src/runtime/src/main.rs
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@ -111,9 +111,6 @@ pub fn main_core0() {
ram::init_alloc_core0(); ram::init_alloc_core0();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
init_gateware();
info!("gateware ident: {}", identifier_read(&mut [0; 64]));
i2c::init(); i2c::init();
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
@ -145,6 +142,9 @@ pub fn main_core0() {
rtio_clocking::init(&mut timer, &cfg); rtio_clocking::init(&mut timer, &cfg);
init_gateware();
info!("gateware ident: {}", identifier_read(&mut [0; 64]));
task::spawn(report_async_rtio_errors()); task::spawn(report_async_rtio_errors());
comms::main(timer, cfg); comms::main(timer, cfg);

7
src/runtime/src/rtio_clocking.rs
View File

@ -68,9 +68,6 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) { fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
unsafe {
pl::csr::sys_crg::pll_reset_write(0);
}
timer.delay_ms(1); timer.delay_ms(1);
let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 }; let locked = unsafe { pl::csr::sys_crg::pll_locked_read() != 0 };
if locked { if locked {
@ -230,9 +227,9 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
_ => setup_si5324(i2c, timer, clk), _ => setup_si5324(i2c, timer, clk),
} }
} }
#[cfg(has_drtio)]
init_drtio(timer);
init_rtio(timer, clk); init_rtio(timer, clk);
#[cfg(has_drtio)]
init_drtio(timer);
} }