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dma: report AXI bus error

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This commit is contained in:
Sebastien Bourdeauducq 2020-07-21 12:47:20 +08:00
parent 21135c6a41
commit 59cf2764ce
1 changed files with 14 additions and 1 deletions
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15
src/gateware/dma.py
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@ -12,7 +12,7 @@ import endianness
AXI_BURST_LEN = 16 AXI_BURST_LEN = 16
class AXIReader(Module): class AXIReader(Module, AutoCSR):
def __init__(self, membus): def __init__(self, membus):
aw = len(membus.ar.addr) aw = len(membus.ar.addr)
dw = len(membus.r.data) dw = len(membus.r.data)
@ -20,6 +20,8 @@ class AXIReader(Module):
self.sink = stream.Endpoint([("address", aw - alignment_bits)]) self.sink = stream.Endpoint([("address", aw - alignment_bits)])
self.source = stream.Endpoint([("data", dw)]) self.source = stream.Endpoint([("data", dw)])
self.bus_error = CSRStatus()
# # # # # #
eop_pending = Signal() eop_pending = Signal()
@ -57,6 +59,17 @@ class AXIReader(Module):
self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1)) self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
] ]
stopped = Signal(reset=1)
self.sync += [
If(self.source.stb & self.source.ack & self.source.eop, stopped.eq(1)),
If(self.sink.stb & self.sink.ack, stopped.eq(0)),
If(stopped & (self.sink.stb & self.sink.ack),
# reset bus error status on new run
self.bus_error.status.eq(0)),
If(membus.r.valid & membus.r.valid & (membus.r.resp != axi.Response.okay),
self.bus_error.status.eq(1))
]
class DMAReader(Module, AutoCSR): class DMAReader(Module, AutoCSR):
def __init__(self, membus, enable): def __init__(self, membus, enable):