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artiq-zynq
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szl: enabled FPU

This commit is contained in:
pca006132 2020-07-02 13:06:36 +08:00
parent 214337387f
commit 57da6f05fd
2 changed files with 14 additions and 1 deletions
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2
src/szl/build.rs
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@ -31,7 +31,7 @@ pub fn compile_unlzma() {
cfg.flag("-ffreestanding"); cfg.flag("-ffreestanding");
cfg.flag("-fPIC"); cfg.flag("-fPIC");
cfg.flag("-fno-stack-protector"); cfg.flag("-fno-stack-protector");
cfg.flag("--target=armv7-unknown-linux"); cfg.flag("--target=armv7-none-eabihf");
cfg.flag("-O2"); cfg.flag("-O2");
let sources = vec![ let sources = vec![

13
src/szl/src/main.rs
View File

@ -1,5 +1,6 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
#![feature(llvm_asm)]
extern crate log; extern crate log;
@ -36,6 +37,18 @@ pub fn main_core0() {
log::set_max_level(log::LevelFilter::Debug); log::set_max_level(log::LevelFilter::Debug);
info!("Simple Zynq Loader starting..."); info!("Simple Zynq Loader starting...");
unsafe {
llvm_asm!("
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, (0b1111<<20)
mcr p15, 0, r1, c1, c0, 2
vmrs r1, fpexc
orr r1, r1, (1<<30)
vmsr fpexc, r1
":::"r1");
}
info!("FPU enabled on Core0");
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
ArmPll::setup(2 * CPU_FREQ); ArmPll::setup(2 * CPU_FREQ);