Gatewre: kasli_soc WRPLL setup
kasli_soc: add --with-wrpll arg to switch from si5324 to si549 kasli_soc: default to use si5435 kasli_soc: add wrpll for all variants kasli_soc: add gtx & main tag nFIQ kasli_soc: add WRPLL_REF_CLK config for firmware
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8e1b62e126
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@ -26,6 +26,7 @@ import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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import wrpll
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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eem_iostandard_dict = {
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@ -118,7 +119,7 @@ class GTPBootstrapClock(Module):
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class GenericStandalone(SoCCore):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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self.acpki = acpki
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self.acpki = acpki
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clk_freq = description["rtio_frequency"]
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clk_freq = description["rtio_frequency"]
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@ -148,6 +149,23 @@ class GenericStandalone(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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self.crg.cd_sys = self.sys_crg.cd_sys
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if with_wrpll:
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=self.clk_synth.se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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if has_grabber:
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@ -204,7 +222,7 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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clk_freq = description["rtio_frequency"]
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clk_freq = description["rtio_frequency"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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@ -221,8 +239,6 @@ class GenericMaster(SoCCore):
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self.config["HW_REV"] = description["hw_rev"]
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.gt_drtio = gtx_7series.GTX(
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self.submodules.gt_drtio = gtx_7series.GTX(
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@ -256,8 +272,22 @@ class GenericMaster(SoCCore):
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.config["HAS_SI5324"] = None
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if with_wrpll:
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self.config["SI5324_SOFT_RESET"] = None
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=self.clk_synth.se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -397,7 +427,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False, with_wrpll=False):
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clk_freq = description["rtio_frequency"]
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.acpki = acpki
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@ -550,14 +580,25 @@ class GenericSatellite(SoCCore):
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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if with_wrpll:
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si5324_clkin=platform.request("cdr_clk"),
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self.submodules.clk_synth = ClockSynthesis(self.platform)
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rx_synchronizer=self.rx_synchronizer,
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self.submodules.wrpll = wrpll.WRPLL(
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ultrascale=False,
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platform=self.platform,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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cd_ref=self.gt_drtio.cd_rtio_rx0,
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self.csr_devices.append("siphaser")
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main_clk_se=self.clk_synth.se)
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self.config["HAS_SI5324"] = None
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self.csr_devices.append("wrpll")
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self.config["SI5324_SOFT_RESET"] = None
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "GTX_CDR"
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else:
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtx0 = self.gt_drtio.gtxs[0]
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gtx0 = self.gt_drtio.gtxs[0]
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platform.add_false_path_constraints(
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platform.add_false_path_constraints(
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@ -587,6 +628,8 @@ def main():
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help="build gateware into the specified directory")
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help="build gateware into the specified directory")
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parser.add_argument("--acpki", default=False, action="store_true",
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parser.add_argument("--acpki", default=False, action="store_true",
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help="enable ACPKI")
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help="enable ACPKI")
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parser.add_argument("--with-wrpll", default=False, action="store_true",
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help="enable WRPLL")
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parser.add_argument("description", metavar="DESCRIPTION",
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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help="JSON system description file")
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args = parser.parse_args()
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args = parser.parse_args()
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@ -604,7 +647,7 @@ def main():
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else:
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else:
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raise ValueError("Invalid DRTIO role")
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raise ValueError("Invalid DRTIO role")
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soc = cls(description, acpki=args.acpki)
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soc = cls(description, acpki=args.acpki, with_wrpll=args.with_wrpll)
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soc.finalize()
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soc.finalize()
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if args.r is not None:
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if args.r is not None:
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