M-Labs/artiq-zynq
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szl: added cache flush and memory barriers.

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Resolves #50.
This commit is contained in:
pca006132 2020-07-14 17:02:42 +08:00
parent 8e3574080c
commit 5149d37be9
1 changed files with 10 additions and 1 deletions
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11
src/szl/src/main.rs
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@ -7,7 +7,11 @@ use core::mem;
use log::{debug, info, error}; use log::{debug, info, error};
use cstr_core::CStr; use cstr_core::CStr;
use libcortex_a9::{enable_fpu, cache::dcci_slice}; use libcortex_a9::{
enable_fpu,
cache::{dcci_slice, iciallu, bpiall},
asm::{dsb, isb},
};
use libboard_zynq::{ use libboard_zynq::{
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}, self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
logger, logger,
@ -57,6 +61,11 @@ pub fn main_core0() {
dcci_slice(unsafe { dcci_slice(unsafe {
core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size()) core::slice::from_raw_parts(ddr.ptr::<u8>(), ddr.size())
}); });
dsb();
iciallu();
bpiall();
dsb();
isb();
// Start core0 only, for compatibility with FSBL. // Start core0 only, for compatibility with FSBL.
info!("executing payload"); info!("executing payload");