gateware: add extra ident info, source version
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parent
e1f493f3ca
commit
500b84aaea
@ -11,6 +11,7 @@
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zynqpkgs = zynq-rs.packages.x86_64-linux;
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zynqpkgs = zynq-rs.packages.x86_64-linux;
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artiqpkgs = artiq.packages.x86_64-linux;
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artiqpkgs = artiq.packages.x86_64-linux;
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llvmPackages_11 = zynq-rs.llvmPackages_11;
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llvmPackages_11 = zynq-rs.llvmPackages_11;
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zynqRev = self.sourceInfo.rev or "unknown";
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rust = zynq-rs.rust;
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rust = zynq-rs.rust;
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rustPlatform = zynq-rs.rustPlatform;
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rustPlatform = zynq-rs.rustPlatform;
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@ -137,6 +138,7 @@
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llvmPackages_11.clang-unwrapped
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llvmPackages_11.clang-unwrapped
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];
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];
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buildPhase = ''
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buildPhase = ''
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export VERSIONEER_ZYNQ_REV=${zynqRev}
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export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
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export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
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export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
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export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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@ -164,6 +166,7 @@
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];
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];
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}
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}
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''
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''
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export VERSIONEER_ZYNQ_REV=${zynqRev}
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python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
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python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
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mkdir -p $out $out/nix-support
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mkdir -p $out $out/nix-support
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cp build/top.bit $out
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cp build/top.bit $out
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@ -386,6 +389,7 @@
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binutils-arm
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binutils-arm
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pre-commit
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pre-commit
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];
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];
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VERSIONEER_ZYNQ_REV="${zynqRev}";
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XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
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XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
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CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
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CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
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ZYNQ_RS = "${zynq-rs}";
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ZYNQ_RS = "${zynq-rs}";
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@ -1,5 +1,9 @@
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import os
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from misoc.integration import cpu_interface
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from misoc.integration import cpu_interface
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def get_zynq_rev():
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return os.getenv("VERSIONEER_ZYNQ_REV", default="unknown")
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def write_csr_file(soc, filename):
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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f.write(cpu_interface.get_csr_rust(
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@ -125,7 +125,11 @@ class EBAZ4205(SoCCore):
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"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
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"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
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)
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)
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ident = self.__class__.__name__
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ident = "{};{};{}".format(
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self.__class__.__name__,
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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@ -21,13 +21,14 @@ from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.gateware.drtio import *
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from artiq.gateware.wrpll import wrpll
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from artiq.gateware.wrpll import wrpll
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from artiq._version import get_version
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import dma
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import dma
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import analyzer
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import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import get_zynq_rev, write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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eem_iostandard_dict = {
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0: "LVDS_25",
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0: "LVDS_25",
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@ -115,7 +116,11 @@ class GenericStandalone(SoCCore):
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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])
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ident = description["variant"]
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ident = "{};{};{}".format(
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description["variant"],
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -229,7 +234,11 @@ class GenericMaster(SoCCore):
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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])
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ident = description["variant"]
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ident = "{};{};{}".format(
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description["variant"],
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -438,7 +447,11 @@ class GenericSatellite(SoCCore):
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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])
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ident = description["variant"]
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ident = "{};{};{}".format(
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description["variant"],
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -19,13 +19,14 @@ from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.gateware.drtio import *
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from artiq._version import get_version
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import dma
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import dma
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import analyzer
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import analyzer
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import acpki
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import acpki
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import drtio_aux_controller
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import drtio_aux_controller
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import zynq_clocking
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import zynq_clocking
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from config import get_zynq_rev, write_csr_file, write_mem_file, write_rustc_cfg_file
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class SMAClkinForward(Module):
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class SMAClkinForward(Module):
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def __init__(self, platform):
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def __init__(self, platform):
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@ -130,7 +131,11 @@ class ZC706(SoCCore):
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platform = zc706.Platform()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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ident = "{};{};{}".format(
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self.__class__.__name__,
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -203,7 +208,11 @@ class _MasterBase(SoCCore):
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platform = zc706.Platform()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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ident = "{};{};{}".format(
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self.__class__.__name__,
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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@ -344,7 +353,11 @@ class _SatelliteBase(SoCCore):
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platform = zc706.Platform()
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platform = zc706.Platform()
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prepare_zc706_platform(platform)
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prepare_zc706_platform(platform)
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ident = self.__class__.__name__
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ident = "{};{};{}".format(
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self.__class__.__name__,
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get_version(),
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get_zynq_rev()[:8]
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)
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if self.acpki:
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if self.acpki:
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ident = "acpki_" + ident
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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