M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

zc706: remove pll_reset

Browse Source
This commit is contained in:
mwojcik 2023-01-12 12:01:43 +08:00
parent 9ac1338a32
commit 4bf99bc63f
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/gateware/zc706.py
View File

@ -29,7 +29,6 @@ import drtio_aux_controller
class SYSCRG(Module, AutoCSR): class SYSCRG(Module, AutoCSR):
def __init__(self, platform): def __init__(self, platform):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus() self.pll_locked = CSRStatus()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
@ -55,7 +54,7 @@ class SYSCRG(Module, AutoCSR):
# VCO @ 1GHz when using 125MHz input # VCO @ 1GHz when using 125MHz input
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=self.cd_sys.clk, i_CLKFBIN=self.cd_sys.clk,
i_RST=self.pll_reset.storage, i_RST=0,
o_CLKFBOUT=sys_clk, o_CLKFBOUT=sys_clk,