M-Labs/artiq-zynq
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satellites: add rtio_dma, connect as cri master

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This commit is contained in:
mwojcik 2023-03-21 15:54:58 +08:00
parent 4c87487fe1
commit 4b1ce1a6ff
2 changed files with 5 additions and 2 deletions
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2
src/gateware/kasli_soc.py
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@ -427,7 +427,7 @@ class GenericSatellite(SoCCore):
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri], [self.drtiosat.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri, [self.local_io.cri] + self.drtio_cri,
enable_routing=True) enable_routing=True)
self.csr_devices.append("cri_con") self.csr_devices.append("cri_con")

5
src/gateware/zc706.py
View File

@ -476,9 +476,12 @@ class _SatelliteBase(SoCCore):
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
self.csr_devices.append("rtio") self.csr_devices.append("rtio")
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
self.csr_devices.append("rtio_dma")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.submodules.cri_con = rtio.CRIInterconnectShared( self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri], [self.drtiosat.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri, [self.local_io.cri] + self.drtio_cri,
enable_routing=True) enable_routing=True)
self.csr_devices.append("cri_con") self.csr_devices.append("cri_con")