From 4aedc2fe61cc541c0811a4445b9783b1d50c00eb Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 12 Jan 2023 16:39:50 +0800 Subject: [PATCH] zc706: fix TSC, PLL parameters --- src/gateware/zc706.py | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 251676b..dacf33d 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -33,38 +33,35 @@ class SYSCRG(Module, AutoCSR): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - rtio_external_clk = Signal() - si5324_out = platform.request("si5324_clkout") - platform.add_period_constraint(si5324_out.p, 8.0) - self.specials += Instance("IBUFDS", - i_I=si5324_out.p, i_IB=si5324_out.n, - o_O=rtio_external_clk) - pll_locked = Signal() sys_clk = Signal() sys4x_clk = Signal() + fb_clk = Signal() self.specials += [ Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0, - i_CLKIN1=rtio_external_clk, + i_CLKIN1=main_clk, + i_CLKINSEL=1, # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=self.cd_sys.clk, + i_CLKFBIN=fb_clk, i_RST=0, - o_CLKFBOUT=sys_clk, + o_CLKFBOUT=fb_clk, - p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=sys4x_clk), + p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, + o_CLKOUT0=sys_clk, + p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, + o_CLKOUT1=sys4x_clk), Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked) ] - self.comb += self.pll_locked.status.eq(pll_locked) + self.comb += self.pll_locked.status.eq(pll_locked) class SMAClkinForward(Module): @@ -173,7 +170,7 @@ class ZC706(SoCCore): self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") @@ -240,7 +237,7 @@ class _MasterBase(SoCCore): rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] @@ -304,7 +301,7 @@ class _MasterBase(SoCCore): fix_serdes_timing_path(self.platform) def add_rtio(self, rtio_channels): - self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels) self.csr_devices.append("rtio_core") @@ -365,7 +362,7 @@ class _SatelliteBase(SoCCore): platform.request("user_sma_mgt") ] - self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock self.submodules.drtio_transceiver = gtx_7series.GTX(