M-Labs/artiq-zynq
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runtime: wait longer for PLL lock

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This commit is contained in:
mwojcik 2023-10-05 12:17:43 +08:00
parent e451598a06
commit 49810da188
1 changed files with 2 additions and 2 deletions
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4
src/runtime/src/rtio_clocking.rs
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@ -76,7 +76,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
} }
// if it's not locked, it will hang at the CSR. // if it's not locked, it will hang at the CSR.
timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");
@ -95,7 +95,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
pl::csr::gt_drtio::stable_clkin_write(1); pl::csr::gt_drtio::stable_clkin_write(1);
} }
timer.delay_ms(20); // wait for CPLL/QPLL/SYS PLL lock timer.delay_ms(50); // wait for CPLL/QPLL/SYS PLL lock
let clk = unsafe { pl::csr::sys_crg::current_clock_read() }; let clk = unsafe { pl::csr::sys_crg::current_clock_read() };
if clk == 1 { if clk == 1 {
info!("SYS CLK switched successfully"); info!("SYS CLK switched successfully");