gateware: fixed zc706/kasli-soc master typos
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bb5af4f156
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45b9d50e70
@ -208,7 +208,6 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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@ -284,10 +283,10 @@ class GenericMaster(SoCCore):
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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mem_size = coreaux.get_mem_size()
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memory_address, size = self.axi2csr.add_port(coreaux.get_tx_port(), mem_size)
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size = coreaux.get_mem_size()
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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# rcv in upper half of the memory, thus added second
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self.axi2csr.add_prot(coreaux.get_rx_port(), mem_size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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@ -315,7 +314,8 @@ class GenericMaster(SoCCore):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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[self.rtio_core.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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@ -337,11 +337,9 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = 125e6 # same thing as with master - pulled from desc?
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# will probably be replaced with rtio_config key as per #1735
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rtio_clk_freq = 125e6
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -229,7 +229,7 @@ class _MasterBase(SoCCore):
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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@ -243,7 +243,7 @@ class _MasterBase(SoCCore):
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core = cdr(DRTIOMaster(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(aux_controller.DRTIOAuxControllerBare(core.link_layer))
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@ -308,7 +308,7 @@ class _MasterBase(SoCCore):
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.rtio.cri, self.rtio_dma.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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