M-Labs/artiq-zynq
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main: set exception vector table addr

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linker: add exceptions start & end symbol
This commit is contained in:
morgan 2024-03-07 12:47:16 +08:00
parent 63bf1c81d4
commit 4455f740d2
3 changed files with 20 additions and 2 deletions
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2
src/libbuild_zynq/link.x
View File

@ -10,7 +10,9 @@ SECTIONS
__text_start = .; __text_start = .;
.text : .text :
{ {
__exceptions_start = .;
KEEP(*(.text.exceptions)); KEEP(*(.text.exceptions));
__exceptions_end = .;
*(.text.boot); *(.text.boot);
*(.text .text.*); *(.text .text.*);
} > SDRAM } > SDRAM

10
src/runtime/src/main.rs
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@ -21,7 +21,7 @@ use libboard_artiq::{identifier_read, logger, pl};
use libboard_zynq::{gic, mpcore, timer::GlobalTimer}; use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
use libconfig::Config; use libconfig::Config;
use libcortex_a9::l2c::enable_l2_cache; use libcortex_a9::l2c::enable_l2_cache;
use libsupport_zynq::ram; use libsupport_zynq::{exception_vectors, ram};
use log::{info, warn}; use log::{info, warn};
mod analyzer; mod analyzer;
@ -38,6 +38,11 @@ mod rtio_mgt;
#[cfg(has_drtio)] #[cfg(has_drtio)]
mod subkernel; mod subkernel;
// linker symbols
extern "C" {
static __exceptions_start: u32;
}
#[cfg(all(feature = "target_kasli_soc", has_drtio))] #[cfg(all(feature = "target_kasli_soc", has_drtio))]
async fn io_expanders_service( async fn io_expanders_service(
i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>, i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>,
@ -77,6 +82,9 @@ static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
#[no_mangle] #[no_mangle]
pub fn main_core0() { pub fn main_core0() {
unsafe {
exception_vectors::set_vector_table(&__exceptions_start as *const u32 as u32);
}
enable_l2_cache(0x8); enable_l2_cache(0x8);
let mut timer = GlobalTimer::start(); let mut timer = GlobalTimer::start();

10
src/satman/src/main.rs
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@ -38,7 +38,7 @@ use libboard_zynq::error_led::ErrorLED;
use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer}; use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer};
use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR}; use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
use libregister::RegisterR; use libregister::RegisterR;
use libsupport_zynq::ram; use libsupport_zynq::{exception_vectors, ram};
use routing::Router; use routing::Router;
use subkernel::Manager as KernelManager; use subkernel::Manager as KernelManager;
@ -48,6 +48,11 @@ mod repeater;
mod routing; mod routing;
mod subkernel; mod subkernel;
// linker symbols
extern "C" {
static __exceptions_start: u32;
}
fn drtiosat_reset(reset: bool) { fn drtiosat_reset(reset: bool) {
unsafe { unsafe {
csr::drtiosat::reset_write(if reset { 1 } else { 0 }); csr::drtiosat::reset_write(if reset { 1 } else { 0 });
@ -827,6 +832,9 @@ static mut LOG_BUFFER: [u8; 1 << 17] = [0; 1 << 17];
#[no_mangle] #[no_mangle]
pub extern "C" fn main_core0() -> i32 { pub extern "C" fn main_core0() -> i32 {
unsafe {
exception_vectors::set_vector_table(&__exceptions_start as *const u32 as u32);
}
enable_l2_cache(0x8); enable_l2_cache(0x8);
let mut timer = GlobalTimer::start(); let mut timer = GlobalTimer::start();