kasli_soc: fix eem iostandards
Hydra zc706-hitl-tests Hydra build #127430 of artiq:zynq:zc706-hitl-tests
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Hydra zc706-hitl-tests Hydra build #127430 of artiq:zynq:zc706-hitl-tests
Details
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3f9bd06468
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@ -70,6 +70,26 @@ class RTIOCRG(Module, AutoCSR):
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]
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]
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eem_iostandard_dict = {
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0: "LVDS_25",
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1: "LVDS_25",
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2: "LVDS",
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3: "LVDS",
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4: "LVDS",
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5: "LVDS",
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6: "LVDS",
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7: "LVDS",
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8: "LVDS_25",
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9: "LVDS_25",
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10: "LVDS",
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11: "LVDS",
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}
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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class GenericStandalone(SoCCore):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.acpki = acpki
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@ -99,7 +119,7 @@ class GenericStandalone(SoCCore):
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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if has_grabber:
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self.grabber_csr_group = []
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"])
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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