M-Labs/artiq-zynq
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gateware: add moninj

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Sebastien Bourdeauducq 2020-04-24 13:36:36 +08:00
parent 4cb73f32aa
commit 3a77ddbcc9
1 changed files with 3 additions and 0 deletions
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zc706.py
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@ -46,6 +46,9 @@ class ZC706(SoCCore):
self.comb += self.rtio.cri.connect(self.rtio_core.cri) self.comb += self.rtio.cri.connect(self.rtio_core.cri)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
def write_csr_file(soc, filename): def write_csr_file(soc, filename):
with open(filename, "w") as f: with open(filename, "w") as f: