M-Labs/artiq-zynq
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turn on bitstream compression

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Sebastien Bourdeauducq 2020-04-11 21:20:38 +08:00
parent 64ac021a36
commit 356860e8dc
1 changed files with 3 additions and 0 deletions
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3
zc706.py
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@ -15,6 +15,9 @@ from artiq.gateware.rtio.phy import ttl_simple
class ZC706(SoCCore): class ZC706(SoCCore):
def __init__(self): def __init__(self):
platform = zc706.Platform() platform = zc706.Platform()
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
SoCCore.__init__(self, platform=platform) SoCCore.__init__(self, platform=platform)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")