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artiq-zynq
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wrpll fw: add delay for reset_plls

morgan 2024-03-27 12:46:50 +08:00
parent 8eeec0bae8
commit 30316d585d
1 changed files with 4 additions and 2 deletions
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6
src/libboard_artiq/src/si549.rs
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@ -463,11 +463,13 @@ pub mod wrpll {
}
}
fn reset_plls() -> Result<(), &'static str> {
fn reset_plls(timer: &mut GlobalTimer) -> Result<(), &'static str> {
*H_INTEGRATOR.lock() = 0;
*M_INTEGRATOR.lock() = 0;
set_adpll(i2c::DCXO::Main, 0)?;
set_adpll(i2c::DCXO::Helper, 0)?;
// wait for adpll to transfer and DCXO to settle
timer.delay_us(200);
Ok(())
}
@ -642,7 +644,7 @@ pub mod wrpll {
if rc {
tag_collector::reset();
reset_plls().expect("failed to reset main and helper PLL");
reset_plls(timer).expect("failed to reset main and helper PLL");
set_base_adpll(timer).expect("failed to set base adpll");
// clear gateware pending flag