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compatibility fixes

master
Sebastien Bourdeauducq 6 months ago
parent
commit
2cc41bbffb
2 changed files with 16 additions and 21 deletions
  1. 1
    1
      maxi_dma.py
  2. 15
    20
      zedboard.py

+ 1
- 1
maxi_dma.py View File

@@ -229,7 +229,7 @@ class DMA_KernelInitiator(Module):
cri.o_address.eq(dout_hw[:16])
]
dout_cases[1] = [
cri.timestamp.eq(engine.dout)
cri.o_timestamp.eq(engine.dout)
]
dout_cases[2] = [cri.o_data.eq(engine.dout)] # only lowest 64 bits


+ 15
- 20
zedboard.py View File

@@ -9,10 +9,8 @@ from misoc.integration.builder import *

from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
from artiq.gateware import eem

from artiq.gateware.rtio.phy import ttl_serdes_7series, ttl_simple
from artiq.gateware import fmcdio_vhdci_eem

from maxi_dma import MAXI_DMA, DMA_KernelInitiator, DMA_Test
from hp_dma import HP_DMA_READ
@@ -99,9 +97,6 @@ class Zedboard(SoCCore):
# ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.dma.bus)
# self.comb += pads_b[0].eq(self.dma.trigger_stb)

plat.add_extension(fmcdio_vhdci_eem.io)
plat.add_connectors(fmcdio_vhdci_eem.connectors)

self.rtio_channels = []

for i in range(4):
@@ -123,10 +118,6 @@ class Zedboard(SoCCore):
self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy))

ttl_phy = ttl_simple.Output
eem.Urukul.add_std(self, 0, 1, ttl_phy, iostandard="LVDS_25")
eem.Urukul.add_std(self, 2, 3, ttl_phy, iostandard="LVDS_25")

self.add_rtio(self.rtio_channels)


@@ -134,9 +125,10 @@ class Zedboard(SoCCore):
self.submodules.rtio_crg = _RTIOCRG()
self.csr_devices.append("rtio_crg")

self.submodules.rtio_core = rtio.Core(rtio_channels)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.csr_devices.append("rtio")

self.submodules.dma = MAXI_DMA(bus=self.ps7.s_axi_acp,
@@ -165,15 +157,18 @@ def main():

soc = Zedboard()

builder = Builder(soc, **builder_argdict(args))
builder.software_packages = []
root_path = os.path.dirname(os.path.abspath(__file__))
builder.add_software_package("libm")
builder.add_software_package("libprintf")
builder.add_software_package("libunwind")
builder.add_software_package("libbase")
builder.add_software_package("runtime", os.path.join(root_path, "firmware/runtime"))
builder.build()
# TODO:
# builder = Builder(soc, **builder_argdict(args))
# builder.software_packages = []
# root_path = os.path.dirname(os.path.abspath(__file__))
# builder.add_software_package("libm")
# builder.add_software_package("libprintf")
# builder.add_software_package("libunwind")
# builder.add_software_package("libbase")
# builder.add_software_package("runtime", os.path.join(root_path, "firmware/runtime"))
# builder.build()

soc.build()


if __name__ == "__main__":

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