libboard_artiq: changed edition to 2018 for async

src/libboard_artiq/Cargo.toml

@@ -2,6 +2,7 @@
 name = "libboard_artiq"
 version = "0.0.0"
 authors = ["M-Labs"]
+edition = "2018"
 
 [lib]
 name = "libboard_artiq"
@@ -19,9 +20,12 @@ log_buffer = { version = "1.2" }
 crc = { version = "1.7", default-features = false }
 core_io = { version = "0.1", features = ["collections"] }
 embedded-hal = "0.2"
+nb = "1.0"
+void = { version = "1", default-features = false }
 
 io = { path = "../libio", features = ["byteorder"] }
 libboard_zynq = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
 libregister = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
 libconfig = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git"}
 libcortex_a9 = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }
+libasync = { git = "https://git.m-labs.hk/M-Labs/zynq-rs.git" }

src/libboard_artiq/src/drtio_routing.rs

@@ -1,6 +1,6 @@
 use libconfig::Config;
 #[cfg(has_drtio_routing)]
-use pl::csr;
+use crate::pl::csr;
 use core::fmt;
 
 use log::{warn, info};

src/libboard_artiq/src/drtioaux.rs

@@ -3,12 +3,12 @@ use crc;
 use core_io::{ErrorKind as IoErrorKind, Error as IoError};
 
 use io::{proto::ProtoRead, proto::ProtoWrite, Cursor};
-use mem::mem::DRTIOAUX_MEM;
-use pl::csr::DRTIOAUX;
-use drtioaux_proto::Error as ProtocolError;
 use libboard_zynq::{timer::GlobalTimer, time::Milliseconds};
+use crate::mem::mem::DRTIOAUX_MEM;
+use crate::pl::csr::DRTIOAUX;
+use crate::drtioaux_proto::Error as ProtocolError;
 
-pub use drtioaux_proto::Packet;
+pub use crate::drtioaux_proto::Packet;
 
 #[derive(Debug)]
 pub enum Error {
@@ -47,7 +47,7 @@ pub fn reset(linkno: u8) {
     }
 }
 
-fn has_rx_error(linkno: u8) -> bool {
+pub fn has_rx_error(linkno: u8) -> bool {
     let linkno = linkno as usize;
     unsafe {
         let error = (DRTIOAUX[linkno].aux_rx_error_read)() != 0;
@@ -58,17 +58,22 @@ fn has_rx_error(linkno: u8) -> bool {
     }
 }
 
-fn swap_byte_order(buf: &mut [u8]) -> () {
+fn copy_with_swap(src: *mut u8, dst: *mut u8, len: isize) {
     // for some reason, everything except checksum arrives
     // with byte order swapped. and it must be sent as such too.
-    // call this for a slice without the checksum included.
+    unsafe {
-    for i in (0..buf.len()).step_by(4) {
+        for i in (0..(len-4)).step_by(4) {
-        let mut temp = buf[i];
+            *dst.offset(i) = *src.offset(i+3);
-        buf[i] = buf[i + 3];
+            *dst.offset(i+1) = *src.offset(i+2);
-        buf[i + 3] = temp;
+            *dst.offset(i+2) = *src.offset(i+1);
-        temp = buf[i + 1];
+            *dst.offset(i+3) = *src.offset(i);
-        buf[i + 1] = buf[i + 2];
+        }
-        buf[i + 2] = temp; 
+        // checksum untouched
+        // unrolled for performance
+        *dst.offset(len-4) = *src.offset(len-4);
+        *dst.offset(len-3) = *src.offset(len-3);
+        *dst.offset(len-2) = *src.offset(len-2);
+        *dst.offset(len-1) = *src.offset(len-1);
     }
 }
 
@@ -82,10 +87,7 @@ fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
             let len = (DRTIOAUX[linkidx].aux_rx_length_read)() as usize;
             // work buffer, as byte order will need to be swapped, cannot be in place
             let mut buf: [u8; 1024] = [0; 1024];
-            for i in 0..len {
+            copy_with_swap(ptr, buf.as_mut_ptr(), len as isize);
-                buf[i] = *(ptr as *mut u8).offset(i as isize);
-            }
-            swap_byte_order(&mut buf[0..len-4]);
             let result = f(&buf[0..len]);
             (DRTIOAUX[linkidx].aux_rx_present_write)(1);
             Ok(Some(result?))
@@ -139,14 +141,12 @@ fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
     let linkno = linkno as usize;
     unsafe {
         while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
-        let pointer = DRTIOAUX_MEM[linkno].base as *mut u8;
+        let ptr = DRTIOAUX_MEM[linkno].base as *mut u8;
         let len = DRTIOAUX_MEM[linkno].size / 2;
         // work buffer, works with unaligned mem access
         let mut buf: [u8; 1024] = [0; 1024]; 
         let len = f(&mut buf[0..len])?;
-        for i in 0..len {
+        copy_with_swap(buf.as_mut_ptr(), ptr, len as isize);
-            *pointer.offset(i as isize) = buf[i];
-        }
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())
@@ -167,8 +167,6 @@ pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
         }
 
         let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
-        let len = writer.position();
-        swap_byte_order(&mut writer.get_mut()[0..len]);
         writer.write_u32(checksum)?;
 
         Ok(writer.position())

src/libboard_artiq/src/lib.rs

@@ -10,6 +10,7 @@ extern crate libboard_zynq;
 extern crate libregister;
 extern crate libconfig;
 extern crate libcortex_a9;
+extern crate libasync;
 extern crate log_buffer;
 
 #[path = "../../../build/pl.rs"]
@@ -22,6 +23,8 @@ pub mod si5324;
 #[cfg(has_drtio)]
 pub mod drtioaux;
 #[cfg(has_drtio)]
+pub mod drtioaux_async;
+#[cfg(has_drtio)]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
 

src/libboard_artiq/src/si5324.rs

@@ -3,7 +3,7 @@ use log::info;
 use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds};
 use embedded_hal::blocking::delay::DelayUs;
 #[cfg(not(si5324_soft_reset))]
-use pl::csr;
+use crate::pl::csr;
 
 type Result<T> = result::Result<T, &'static str>;