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wrpll_refclk: MMCM -> mmcm

morgan 2024-03-26 16:24:31 +08:00
parent be6c1474b0
commit 240b80309e
1 changed files with 2 additions and 2 deletions
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4
src/libboard_artiq/src/si549.rs
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@ -729,7 +729,7 @@ pub mod wrpll_refclk {
fn read(address: u8) -> u16 {
set_addr(address);
set_enable(true);
// Set DADDR on the MMCM and assert DEN for one clock cycle
// Set DADDR on the mmcm and assert DEN for one clock cycle
one_clock_cycle();
set_enable(false);
@ -745,7 +745,7 @@ pub mod wrpll_refclk {
set_data(value);
set_write_enable(true);
set_enable(true);
// Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
// Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
one_clock_cycle();
set_write_enable(false);