From 21eb1cab1a70fc71fdc0665bc94d90009feb8e51 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 14 Oct 2021 15:43:51 +0800 Subject: [PATCH 1/2] zc706: added dummy spi in place of sdio --- src/gateware/zc706.py | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 8e99bac..9f87181 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -93,10 +93,7 @@ pmod1_33 = [ ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")), ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")), ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")), - ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")), - ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")), - ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")), - ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")), + # rest removed for use with dummy spi ] _ams101_dac = [ @@ -109,6 +106,17 @@ _ams101_dac = [ ) ] +_dummy_spi = [ + ("dummy_spi", 0, + # PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock + Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")), + Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")), + Subsignal("mosi", Pins("AC18"), IOStandard("LVCMOS25")), + Subsignal("cs_n", Pins("AC19"), IOStandard("LVCMOS25")), + IOStandard("LVCMOS25") + ) +] + def prepare_zc706_platform(platform): platform.toolchain.bitstream_commands.extend([ @@ -459,6 +467,7 @@ class _NIST_CLOCK_RTIO: platform.add_extension(leds_fmc33) platform.add_extension(pmod1_33) platform.add_extension(_ams101_dac) + platform.add_extension(_dummy_spi) rtio_channels = [] @@ -506,10 +515,10 @@ class _NIST_CLOCK_RTIO: rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) - # no SDIO on PL side, PMOD1_1 placeholder instead - phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 1)) + # no SDIO on PL side, dummy SPI placeholder instead + phy = spi2.SPIMaster(platform.request("dummy_spi")) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy From 0b27349ec42dc24a3ba16290a02be986b934f528 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Thu, 14 Oct 2021 16:37:13 +0800 Subject: [PATCH 2/2] dummy_spi -> pmod_spi --- src/gateware/zc706.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 9f87181..aceb2e9 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -106,8 +106,8 @@ _ams101_dac = [ ) ] -_dummy_spi = [ - ("dummy_spi", 0, +_pmod_spi = [ + ("pmod_spi", 0, # PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")), Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")), @@ -467,7 +467,7 @@ class _NIST_CLOCK_RTIO: platform.add_extension(leds_fmc33) platform.add_extension(pmod1_33) platform.add_extension(_ams101_dac) - platform.add_extension(_dummy_spi) + platform.add_extension(_pmod_spi) rtio_channels = [] @@ -516,7 +516,7 @@ class _NIST_CLOCK_RTIO: phy, ififo_depth=128)) # no SDIO on PL side, dummy SPI placeholder instead - phy = spi2.SPIMaster(platform.request("dummy_spi")) + phy = spi2.SPIMaster(platform.request("pmod_spi")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))