From 229cef0a07d04ab2648f902790169a7190145b7a Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 14:32:26 +0800 Subject: [PATCH] zc706: change RTIO CRG to SYS --- src/gateware/zc706.py | 53 ++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 6bb7b4c..10a2039 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -27,48 +27,45 @@ import acpki import drtio_aux_controller -class RTIOCRG(Module, AutoCSR): - def __init__(self, platform, rtio_internal_clk): - self.clock_sel = CSRStorage() +class SYSCRG(Module, AutoCSR): + def __init__(self, platform): self.pll_reset = CSRStorage(reset=1) self.pll_locked = CSRStatus() - self.clock_domains.cd_rtio = ClockDomain() - self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) rtio_external_clk = Signal() - user_sma_clock = platform.request("user_sma_clock") - platform.add_period_constraint(user_sma_clock.p, 8.0) + si5324_out = platform.request("si5324_clkout") + platform.add_period_constraint(si5324_out.p, 8.0) self.specials += Instance("IBUFDS", - i_I=user_sma_clock.p, i_IB=user_sma_clock.n, + i_I=si5324_out.p, i_IB=si5324_out.n, o_O=rtio_external_clk) pll_locked = Signal() - rtio_clk = Signal() - rtiox4_clk = Signal() + sys_clk = Signal() + sys4x_clk = Signal() self.specials += [ Instance("PLLE2_ADV", p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_REF_JITTER1=0.01, - p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0, - i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk, - # Warning: CLKINSEL=0 means CLKIN2 is selected - i_CLKINSEL=~self.clock_sel.storage, + p_CLKIN1_PERIOD=8.0, + i_CLKIN1=rtio_external_clk, # VCO @ 1GHz when using 125MHz input p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1, - i_CLKFBIN=self.cd_rtio.clk, + i_CLKFBIN=self.cd_sys.clk, i_RST=self.pll_reset.storage, - o_CLKFBOUT=rtio_clk, + o_CLKFBOUT=sys_clk, p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0, - o_CLKOUT0=rtiox4_clk), - Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk), - Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk), - AsyncResetSynchronizer(self.cd_rtio, ~pll_locked), - MultiReg(pll_locked, self.pll_locked.status) + o_CLKOUT0=sys4x_clk), + Instance("BUFG", i_I=sys_clk, o_O=self.cd_sys.clk), + Instance("BUFG", i_I=sys4x_clk, o_O=self.cd_sys4x.clk), + AsyncResetSynchronizer(self.cd_sys, ~pll_locked) ] + self.comb += self.pll_locked.status.eq(pll_locked) class SMAClkinForward(Module): @@ -150,15 +147,11 @@ class ZC706(SoCCore): ident = self.__class__.__name__ if self.acpki: ident = "acpki_" + ident - SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) + SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) - self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) - self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg_clock_sel"] = None - self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) - self.platform.add_false_path_constraints( - self.ps7.cd_sys.clk, - self.rtio_crg.cd_rtio.clk) + self.submodules.sys_crg = SYSCRG(self.platform) + self.csr_devices.append("sys_crg") + self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.) def add_rtio(self, rtio_channels): self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) @@ -616,6 +609,7 @@ class _NIST_QC2_RTIO: class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): def __init__(self, acpki, drtio100mhz): ZC706.__init__(self, acpki) + self.submodules += SMAClkinForward(self.platform) _NIST_CLOCK_RTIO.__init__(self) class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): @@ -631,6 +625,7 @@ class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): class NIST_QC2(ZC706, _NIST_QC2_RTIO): def __init__(self, acpki, drtio100mhz): ZC706.__init__(self, acpki) + self.submodules += SMAClkinForward(self.platform) _NIST_QC2_RTIO.__init__(self) class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):