sync with zc706 repos
This commit is contained in:
parent
b123e15b3c
commit
22531b14c0
10
Cargo.lock
generated
10
Cargo.lock
generated
@ -150,7 +150,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#614b1ef350edd8576fc71292fc89cf79a1810aba"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#83ff37e10e721c436246fbf4a945af9516121d00"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -162,7 +162,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#614b1ef350edd8576fc71292fc89cf79a1810aba"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#83ff37e10e721c436246fbf4a945af9516121d00"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -177,7 +177,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#614b1ef350edd8576fc71292fc89cf79a1810aba"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#83ff37e10e721c436246fbf4a945af9516121d00"
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dependencies = [
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"bit_field",
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"libregister",
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@ -186,7 +186,7 @@ dependencies = [
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#614b1ef350edd8576fc71292fc89cf79a1810aba"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#83ff37e10e721c436246fbf4a945af9516121d00"
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dependencies = [
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"bit_field",
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"vcell",
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@ -196,7 +196,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#614b1ef350edd8576fc71292fc89cf79a1810aba"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#83ff37e10e721c436246fbf4a945af9516121d00"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -1,8 +1,5 @@
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ENTRY(_boot_cores);
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STACK_SIZE = 0x8000;
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HEAP_SIZE = 0x1000000;
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/* Provide some defaults */
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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@ -15,7 +12,7 @@ PROVIDE(FIQ = Reset);
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MEMORY
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{
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SDRAM : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
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SDRAM : ORIGIN = 0x00100000, LENGTH = 0x1FF00000
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}
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SECTIONS
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@ -37,35 +34,41 @@ SECTIONS
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*(.data .data.*);
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} > SDRAM
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.bss (NOLOAD) : ALIGN(0x4000)
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.bss (NOLOAD) : ALIGN(4)
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{
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/* Aligned to 16 kB */
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__bss_start = .;
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KEEP(*(.bss.l1_table));
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*(.bss .bss.*);
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. = ALIGN(4);
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__bss_end = .;
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} > SDRAM
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__bss_start = ADDR(.bss);
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__bss_end = ADDR(.bss) + SIZEOF(.bss);
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.heap (NOLOAD) : ALIGN(0x1000)
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.heap (NOLOAD) : ALIGN(8)
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{
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. += HEAP_SIZE;
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__heap_start = .;
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. += 0x1000000;
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__heap_end = .;
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} > SDRAM
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__heap_start = ADDR(.heap);
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__heap_end = ADDR(.heap) + SIZEOF(.heap);
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.stack (NOLOAD) : ALIGN(0x1000)
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.stack1 (NOLOAD) : ALIGN(8)
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{
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. += STACK_SIZE;
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__stack1_end = .;
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. += 0x1000000;
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__stack1_start = .;
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} > SDRAM
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__stack_end = ADDR(.stack);
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__stack_start = ADDR(.stack) + SIZEOF(.stack);
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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.stack0 (NOLOAD) : ALIGN(8)
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{
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__stack0_end = .;
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. += 0x1000000;
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__stack0_start = .;
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} > SDRAM
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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}
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@ -194,7 +194,7 @@ pub fn main(timer: GlobalTimer) {
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Sockets::init(32);
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let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start(8192)));
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let control: Rc<RefCell<kernel::Control>> = Rc::new(RefCell::new(kernel::Control::start()));
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task::spawn(async move {
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loop {
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let stream = TcpStream::accept(1381, 2048, 2048).await.unwrap();
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@ -21,15 +21,14 @@ static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<Message>>> = Mutex::new
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static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<Message>>> = Mutex::new(None);
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pub struct Control {
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core1: Core1<Vec<u32>>,
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core1: Core1,
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pub tx: sync_channel::Sender<Message>,
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pub rx: sync_channel::Receiver<Message>,
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}
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impl Control {
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pub fn start(stack_size: usize) -> Self {
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let stack = vec![0; stack_size / 4];
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let core1 = Core1::start(stack);
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pub fn start() -> Self {
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let core1 = Core1::start();
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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45
szl/link.x
45
szl/link.x
@ -1,7 +1,5 @@
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ENTRY(_boot_cores);
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STACK_SIZE = 0x8000;
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/* Provide some defaults */
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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@ -14,9 +12,9 @@ PROVIDE(FIQ = Reset);
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MEMORY
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{
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/* 256 kB On-Chip Memory */
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OCM : ORIGIN = 0, LENGTH = 0x30000
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OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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/* 256 kB On-Chip Memory */
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OCM : ORIGIN = 0, LENGTH = 0x30000
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OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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}
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SECTIONS
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@ -38,27 +36,34 @@ SECTIONS
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*(.data .data.*);
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} > OCM
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.bss (NOLOAD) : ALIGN(0x4000)
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.bss (NOLOAD) : ALIGN(4)
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{
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/* Aligned to 16 kB */
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__bss_start = .;
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KEEP(*(.bss.l1_table));
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*(.bss .bss.*);
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. = ALIGN(4);
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__bss_end = .;
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} > OCM
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__bss_start = ADDR(.bss);
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__bss_end = ADDR(.bss) + SIZEOF(.bss);
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.stack (NOLOAD) : ALIGN(0x1000) {
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. += STACK_SIZE;
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.stack1 (NOLOAD) : ALIGN(8)
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{
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__stack1_end = .;
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. += 0x4000;
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__stack1_start = .;
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} > OCM
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__stack_end = ADDR(.stack);
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__stack_start = ADDR(.stack) + SIZEOF(.stack);
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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.stack0 (NOLOAD) : ALIGN(8)
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{
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__stack0_end = .;
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. += 0x4000;
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__stack0_start = .;
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} > OCM
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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}
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use libsupport_zynq::{boot, logger};
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static mut STACK_CORE1: [u32; 512] = [0; 512];
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extern "C" {
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fn unlzma_simple(buf: *const u8, in_len: i32,
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output: *mut u8,
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@ -49,8 +47,7 @@ pub fn main_core0() {
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if result < 0 {
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error!("decompression failed");
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} else {
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
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boot::Core1::start(core1_stack);
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boot::Core1::start();
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info!("executing payload");
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unsafe {
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(mem::transmute::<*mut u8, fn()>(ddr.ptr::<u8>()))();
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