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artiq-zynq
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Cal skew: use static must

morgan 2024-04-09 12:47:09 +08:00
parent 611c08262f
commit 20732c0de1
1 changed files with 12 additions and 6 deletions
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18
src/libboard_artiq/src/si549.rs
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@ -352,9 +352,9 @@ pub mod wrpll {
use super::*;
#[cfg(wrpll_ref_clk = "GT_CDR")]
static TAG_OFFSET: Mutex<u32> = Mutex::new(19050);
static mut TAG_OFFSET: u32 = 19050;
#[cfg(wrpll_ref_clk = "SMA_CLKIN")]
static TAG_OFFSET: Mutex<u32> = Mutex::new(0);
static mut TAG_OFFSET: u32 = 0;
static mut REF_TAG: u32 = 0;
static mut REF_TAG_READY: bool = false;
static mut MAIN_TAG: u32 = 0;
@ -394,12 +394,14 @@ pub mod wrpll {
#[cfg(feature = "calibrate_wrpll_skew")]
pub fn set_tag_offset(offset: u32) {
*TAG_OFFSET.lock() = offset;
unsafe {
TAG_OFFSET = offset;
}
}
#[cfg(feature = "calibrate_wrpll_skew")]
pub fn get_tag_offset() -> u32 {
*TAG_OFFSET.lock()
unsafe { TAG_OFFSET }
}
pub fn get_period_error() -> i32 {
@ -415,8 +417,12 @@ pub mod wrpll {
pub fn get_phase_error() -> i32 {
// MAIN_TAG(n) - REF_TAG(n) - TAG_OFFSET mod BEATING_PERIOD
let mut phase_error =
unsafe { MAIN_TAG.overflowing_sub(REF_TAG).0.rem_euclid(BEATING_PERIOD as u32) as i32 };
let mut phase_error = unsafe {
MAIN_TAG
.overflowing_sub(REF_TAG + TAG_OFFSET)
.0
.rem_euclid(BEATING_PERIOD as u32) as i32
};
// mapping tags from [0, 2π] -> [-π, π]
if phase_error > BEATING_HALFPERIOD {