kasli_soc: fixes to make satellite variant work
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cd3e46fb3a
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@ -24,7 +24,7 @@ from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import aux_controller
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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@ -258,7 +258,7 @@ class GenericMaster(SoCCore):
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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@ -337,6 +337,11 @@ class GenericSatellite(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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# todo: replace rtio_crg with rtioclockmultiplier
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# put range(1) to make it work while axi doesn't support anything but P2P
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -345,14 +350,6 @@ class GenericSatellite(SoCCore):
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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@ -400,7 +397,7 @@ class GenericSatellite(SoCCore):
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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coreaux = cdr(aux_controller.DRTIOAuxControllerAxi(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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@ -427,7 +424,7 @@ class GenericSatellite(SoCCore):
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, self.rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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@ -442,18 +439,14 @@ class GenericSatellite(SoCCore):
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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rtio_clk_period = 1e9/rtio_clk_freq
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self.rustc_cfg["rtio_frequency"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.clk125_div2, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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ultrascale=False,
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rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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@ -461,12 +454,12 @@ class GenericSatellite(SoCCore):
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self.rustc_cfg["has_siphaser"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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gtx = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtx.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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gtx0 = self.drtio_transceiver.gtxs[0]
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platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtx.txoutclk, gtx.rxoutclk)
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gtx0.txoutclk, gtx0.rxoutclk)
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for gtx in self.drtio_transceiver.gtxs[1:]:
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platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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@ -475,9 +468,7 @@ class GenericSatellite(SoCCore):
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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# no RTIO CRG here
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def write_mem_file(soc, filename):
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@ -9,7 +9,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from migen_axi.interconnect import sram, axi
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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@ -129,7 +128,6 @@ class ZC706(SoCCore):
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class _MasterBase(SoCCore):
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mem_map = {
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"drtioaux": 0x40000000,
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}
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mem_map.update(SoCCore.mem_map)
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