diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index aabe546..ce8a6b9 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -142,7 +142,6 @@ def prepare_zc706_platform(platform): class ZC706(SoCCore): def __init__(self, acpki=False): self.acpki = acpki - self.rustc_cfg = dict() platform = zc706.Platform() prepare_zc706_platform(platform) @@ -154,7 +153,7 @@ class ZC706(SoCCore): self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk) self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg_clock_sel"] = None + self.config["has_rtio_crg_clock_sel"] = None self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) self.platform.add_false_path_constraints( self.ps7.cd_sys.clk, @@ -166,14 +165,14 @@ class ZC706(SoCCore): self.csr_devices.append("rtio_core") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["ki_impl"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["ki_impl"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -196,7 +195,6 @@ class ZC706(SoCCore): class _MasterBase(SoCCore): def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki - self.rustc_cfg = dict() platform = zc706.Platform() prepare_zc706_platform(platform) @@ -258,18 +256,18 @@ class _MasterBase(SoCCore): memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size) self.axi2csr.register_port(coreaux.get_rx_port(), mem_size) self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) - self.rustc_cfg["has_drtio"] = None - self.rustc_cfg["has_drtio_routing"] = None + self.config["has_drtio"] = None + self.config["has_drtio_routing"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") - self.rustc_cfg["has_si5324"] = None - self.rustc_cfg["si5324_as_synthesizer"] = None + self.config["has_si5324"] = None + self.config["si5324_as_synthesizer"] = None rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel @@ -297,14 +295,14 @@ class _MasterBase(SoCCore): self.csr_devices.append("rtio_core") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["ki_impl"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["ki_impl"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -331,7 +329,6 @@ class _MasterBase(SoCCore): class _SatelliteBase(SoCCore): def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki - self.rustc_cfg = dict() platform = zc706.Platform() prepare_zc706_platform(platform) @@ -405,13 +402,13 @@ class _SatelliteBase(SoCCore): # and registered in PS interface # manually, because software refers to rx/tx by halves of entire memory block, not names self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) - self.rustc_cfg["has_drtio"] = None - self.rustc_cfg["has_drtio_routing"] = None + self.config["has_drtio"] = None + self.config["has_drtio_routing"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtiorep", drtiorep_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.config["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( @@ -424,8 +421,8 @@ class _SatelliteBase(SoCCore): self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") - self.rustc_cfg["has_si5324"] = None - self.rustc_cfg["has_siphaser"] = None + self.config["has_si5324"] = None + self.config["has_siphaser"] = None rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel @@ -445,7 +442,7 @@ class _SatelliteBase(SoCCore): self.submodules.rtio_crg = RTIOClockMultiplier(self.sys_clk_freq) self.csr_devices.append("rtio_crg") - self.rustc_cfg["has_rtio_crg"] = None + self.config["has_rtio_crg"] = None fix_serdes_timing_path(self.platform) def add_rtio(self, rtio_channels): @@ -453,14 +450,14 @@ class _SatelliteBase(SoCCore): self.csr_devices.append("rtio_moninj") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["ki_impl"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["ki_impl"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -669,11 +666,14 @@ def write_mem_file(soc, filename): def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: - for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)): - if v is None: - f.write("{}\n".format(k)) - else: - f.write("{}=\"{}\"\n".format(k, v)) + for name, origin, busword, obj in soc.get_csr_regions(): + f.write("has_{}\n".format(name.lower())) + for name, value in soc.get_constants(): + if name.upper().startswith("CONFIG_"): + if value is None: + f.write("{}\n".format(name.lower()[7:])) + else: + f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) def main():