M-Labs/artiq-zynq
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dma: fix and cleanup test

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This commit is contained in:
Sebastien Bourdeauducq 2020-07-13 18:58:08 +08:00
parent 5c3c3c26b5
commit 12ba867268
1 changed files with 1 additions and 2 deletions
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3
src/gateware/test_dma.py
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@ -26,7 +26,6 @@ class AXIMemorySim:
while True: while True:
if len(self.queue) < self.max_queue: if len(self.queue) < self.max_queue:
request = yield from self.bus.read_ar() request = yield from self.bus.read_ar()
print(request.addr)
self.queue.append(request) self.queue.append(request)
else: else:
yield yield
@ -44,7 +43,7 @@ class AXIMemorySim:
if request.addr % self.align: if request.addr % self.align:
raise ValueError raise ValueError
addr = request.addr//self.align + i addr = request.addr//self.align + i
if addr < len(self.queue): if addr < len(self.data):
data = self.data[addr] data = self.data[addr]
else: else:
data = 0 data = 0