kasli_soc: fix master rtio clock

src/gateware/kasli_soc.py

@@ -210,6 +210,7 @@ class GenericStandalone(SoCCore):
 class GenericMaster(SoCCore):
     def __init__(self, description, acpki=False):
         sys_clk_freq = 125e6
+        rtio_clk_freq = 125e6
 
         self.acpki = acpki
         self.rustc_cfg = dict()
@@ -237,12 +238,8 @@ class GenericMaster(SoCCore):
         self.csr_devices.append("drtio_transceiver")
 
         self.crg = self.ps7 # HACK for eem_7series to find the clock
-        self.submodules.rtio_crg = RTIOCRG(self.platform)
+        self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
         self.csr_devices.append("rtio_crg")
-        self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
-        self.platform.add_false_path_constraints(
-            self.ps7.cd_sys.clk,
-            self.rtio_crg.cd_rtio.clk)
 
         self.rtio_channels = []
         has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
@@ -330,9 +327,6 @@ class GenericMaster(SoCCore):
         if has_grabber:
             self.rustc_cfg["has_grabber"] = None
             self.add_csr_group("grabber", self.grabber_csr_group)
-            for grabber in self.grabber_csr_group:
-                self.platform.add_false_path_constraints(
-                    self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
 
 
 class GenericSatellite(SoCCore):