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@ -210,6 +210,7 @@ class GenericStandalone(SoCCore): |
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class GenericMaster(SoCCore): |
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def __init__(self, description, acpki=False): |
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sys_clk_freq = 125e6 |
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rtio_clk_freq = 125e6 |
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self.acpki = acpki |
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self.rustc_cfg = dict() |
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@ -237,12 +238,8 @@ class GenericMaster(SoCCore): |
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self.csr_devices.append("drtio_transceiver") |
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self.crg = self.ps7 # HACK for eem_7series to find the clock |
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self.submodules.rtio_crg = RTIOCRG(self.platform) |
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq) |
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self.csr_devices.append("rtio_crg") |
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) |
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self.platform.add_false_path_constraints( |
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self.ps7.cd_sys.clk, |
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self.rtio_crg.cd_rtio.clk) |
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self.rtio_channels = [] |
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) |
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@ -330,9 +327,6 @@ class GenericMaster(SoCCore): |
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if has_grabber: |
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self.rustc_cfg["has_grabber"] = None |
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self.add_csr_group("grabber", self.grabber_csr_group) |
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for grabber in self.grabber_csr_group: |
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self.platform.add_false_path_constraints( |
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk) |
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class GenericSatellite(SoCCore): |
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